sys/dev/pci/machfb.c

1055

regr(sc, r->offset), r->name);

sys/dev/pci/machfb.c

1161

regw(sc, GEN_TEST_CNTL, regr(sc, GEN_TEST_CNTL) & ~GUI_ENGINE_ENABLE);

sys/dev/pci/machfb.c

1164

regw(sc, GEN_TEST_CNTL, regr(sc, GEN_TEST_CNTL) | GUI_ENGINE_ENABLE);

sys/dev/pci/machfb.c

1168

regw(sc, BUS_CNTL, regr(sc, BUS_CNTL) | BUS_HOST_ERR_ACK |

sys/dev/pci/machfb.c

1241

regw(sc, DAC_CNTL, regr(sc, DAC_CNTL) | DAC_8BIT_EN);

sys/dev/pci/machfb.c

1246

regw(sc, DAC_CNTL, regr(sc, DAC_CNTL) | DAC_8BIT_EN);

sys/dev/pci/machfb.c

1252

regw(sc, CRTC_INT_CNTL, regr(sc, CRTC_INT_CNTL) & ~0x20);

sys/dev/pci/machfb.c

1266

regw(sc, CRTC_OFF_PITCH, (regr(sc, CRTC_OFF_PITCH) & 0xfff00000) |

sys/dev/pci/machfb.c

1364

DPRINTF("DSP_ON_OFF %08x\n", regr(sc, DSP_ON_OFF));

sys/dev/pci/machfb.c

1365

DPRINTF("DSP_CONFIG %08x\n", regr(sc, DSP_CONFIG));

sys/dev/pci/machfb.c

1370

DPRINTF("DSP_ON_OFF %08x\n", regr(sc, DSP_ON_OFF));

sys/dev/pci/machfb.c

1371

DPRINTF("DSP_CONFIG %08x\n", regr(sc, DSP_CONFIG));

sys/dev/pci/machfb.c

1430

clockreg = regr(sc, CLOCK_CNTL);

sys/dev/pci/machfb.c

2108

reg = regr(sc, CRTC_GEN_CNTL);

sys/dev/pci/machfb.c

2113

reg = regr(sc, CRTC_GEN_CNTL);

sys/dev/pci/machfb.c

355

reg = regr(sc, CLOCK_CNTL);

sys/dev/pci/machfb.c

378

while ((regr(sc, FIFO_STAT) & 0xffff) > (0x8000 >> v))

sys/dev/pci/machfb.c

386

while ((regr(sc, GUI_STAT) & 1) != 0)

sys/dev/pci/machfb.c

566

sc->memtype = (regr(sc, CONFIG_STAT0) >> 3) & 0x07;

sys/dev/pci/machfb.c

568

sc->memtype = regr(sc, CONFIG_STAT0) & 0x07;

sys/dev/pci/machfb.c

572

reg = regr(sc, CLOCK_CNTL);

sys/dev/pci/machfb.c

598

id = regr(sc, CONFIG_CHIP_ID) & 0xffff;

sys/dev/pci/machfb.c

618

sc->sc_gen_cntl = regr(sc, CRTC_GEN_CNTL);

sys/dev/pci/machfb.c

803

reg = regr(sc, BUS_CNTL);

sys/dev/pci/machfb.c

874

tmp = regr(sc, MEM_CNTL);

sys/dev/pci/machfb.c

939

hdisplay = regr(sc, CRTC_H_TOTAL_DISP);

sys/dev/pci/machfb.c

940

hsync_end = regr(sc, CRTC_H_SYNC_STRT_WID);

sys/dev/pci/machfb.c

941

vdisplay = regr(sc, CRTC_V_TOTAL_DISP);

sys/dev/pci/machfb.c

942

vsync_end = regr(sc, CRTC_V_SYNC_STRT_WID);

sys/dev/pci/machfb.c

943

clk_ctl = regr(sc, CLOCK_CNTL);