sys/arch/arm/marvell/armadaxp.c

1087

reg = read_mlmbreg(MVSOC_MLMB_CIB_CTRL_CFG);

sys/arch/arm/marvell/armadaxp.c

1092

reg = read_mlmbreg(MVSOC_MLMB_CFU_FAB_CTRL);

sys/arch/arm/marvell/armadaxp.c

1097

reg = read_mlmbreg(MVSOC_MLMB_CFU_CFG);

sys/arch/arm/marvell/armadaxp.c

1138

reg = read_mlmbreg(MVSOC_MLMB_WCR(i));

sys/arch/arm/marvell/armadaxp.c

929

reg = read_mlmbreg(ARMADAXP_L2_CFU);

sys/arch/arm/marvell/dove.c

55

#define read_dbreg read_mlmbreg

sys/arch/arm/marvell/kirkwood.c

174

write_mlmbreg(reg, read_mlmbreg(reg) | irq_mask);

sys/arch/arm/marvell/kirkwood.c

186

write_mlmbreg(reg, read_mlmbreg(reg) & ~irq_mask);

sys/arch/arm/marvell/kirkwood.c

211

uint32_t causelow = read_mlmbreg(KIRKWOOD_MLMB_MICLR);

sys/arch/arm/marvell/kirkwood.c

212

uint32_t pendinglow = read_mlmbreg(KIRKWOOD_MLMB_MIRQIMLR);

sys/arch/arm/marvell/kirkwood.c

219

uint32_t causehigh = read_mlmbreg(KIRKWOOD_MLMB_MICHR);

sys/arch/arm/marvell/kirkwood.c

220

uint32_t pendinghigh = read_mlmbreg(KIRKWOOD_MLMB_MIRQIMHR);

sys/arch/arm/marvell/kirkwood.c

298

val = read_mlmbreg(MVSOC_MLMB_CLKGATING);

sys/arch/arm/marvell/mv78xx0.c

142

read_mlmbreg(MV78XX0_ICI_IRQIMR(group)) | irq_mask);

sys/arch/arm/marvell/mv78xx0.c

152

read_mlmbreg(MV78XX0_ICI_IRQIMR(group)) & ~irq_mask);

sys/arch/arm/marvell/mv78xx0.c

166

mlmbim = read_mlmbreg(MVSOC_MLMB_MLMBIMR);

sys/arch/arm/marvell/mv78xx0.c

188

pending = read_mlmbreg(MV78XX0_ICI_MICR(0)) &

sys/arch/arm/marvell/mv78xx0.c

189

read_mlmbreg(MV78XX0_ICI_IRQIMR(0));

sys/arch/arm/marvell/mv78xx0.c

193

pending = read_mlmbreg(MV78XX0_ICI_MICR(1)) &

sys/arch/arm/marvell/mv78xx0.c

194

read_mlmbreg(MV78XX0_ICI_IRQIMR(1));

sys/arch/arm/marvell/mvsoc.c

1250

*base = read_mlmbreg(MVSOC_MLMB_IRBAR) &

sys/arch/arm/marvell/mvsoc.c

1362

sizereg = read_mlmbreg(MVSOC_MLMB_WINCR(i));

sys/arch/arm/marvell/mvsoc.c

1375

baseaddrreg = read_mlmbreg(MVSOC_MLMB_WINBAR(i));

sys/arch/arm/marvell/mvsoc.c

1441

ctrlreg = read_mlmbreg(MVSOC_MLMB_WCR(i));

sys/arch/arm/marvell/mvsoc.c

1445

basereg = read_mlmbreg(MVSOC_MLMB_WBR(i));

sys/arch/arm/marvell/mvsoc.c

1466

reg = read_mlmbreg(MVSOC_MLMB_WCR(i));

sys/arch/arm/marvell/mvsoc.c

1472

reg = read_mlmbreg(MVSOC_MLMB_WBR(i));

sys/arch/arm/marvell/mvsoc_intr.c

115

read_mlmbreg(MVSOC_MLMB_MLMBICR) & ~irq_mask);

sys/arch/arm/marvell/mvsoc_intr.c

117

read_mlmbreg(MVSOC_MLMB_MLMBIMR) | irq_mask);

sys/arch/arm/marvell/mvsoc_intr.c

127

read_mlmbreg(MVSOC_MLMB_MLMBIMR) & ~irq_mask);

sys/arch/arm/marvell/mvsoc_intr.c

136

read_mlmbreg(MVSOC_MLMB_MLMBICR) & read_mlmbreg(MVSOC_MLMB_MLMBIMR);

sys/arch/arm/marvell/mvsoc_space.c

437

remap = read_mlmbreg(MVSOC_MLMB_WRLR(window)) &

sys/arch/arm/marvell/mvsoc_space.c

440

(read_mlmbreg(MVSOC_MLMB_WRHR(window)) << 16) << 16;

sys/arch/arm/marvell/mvsoctmr.c

174

rstoutn = read_mlmbreg(MVSOC_MLMB_RSTOUTNMASKR);

sys/arch/arm/marvell/orion.c

133

read_mlmbreg(ORION_MLMB_MIRQIMR) | irq_mask);

sys/arch/arm/marvell/orion.c

142

read_mlmbreg(ORION_MLMB_MIRQIMR) & ~irq_mask);

sys/arch/arm/marvell/orion.c

168

read_mlmbreg(ORION_MLMB_MICR) & read_mlmbreg(ORION_MLMB_MIRQIMR);

sys/arch/arm/marvell/pci_machdep.c

469

remapl = read_mlmbreg(MVSOC_MLMB_WRLR(window));

sys/arch/arm/marvell/pci_machdep.c

470

remaph = read_mlmbreg(MVSOC_MLMB_WRHR(window));

sys/arch/evbarm/armadaxp/armadaxp_machdep.c

208

if ((read_mlmbreg(MVSOC_MLMB_WCR(i)) &

sys/arch/evbarm/armadaxp/armadaxp_machdep.c

472

*start = read_mlmbreg(MVSOC_MLMB_WRLR(win)) |

sys/arch/evbarm/armadaxp/armadaxp_machdep.c

473

((read_mlmbreg(MVSOC_MLMB_WRHR(win)) << 16) << 16);

sys/arch/evbarm/marvell/marvell_machdep.c

846

*start = read_mlmbreg(MVSOC_MLMB_WRLR(win)) |

sys/arch/evbarm/marvell/marvell_machdep.c

847

((read_mlmbreg(MVSOC_MLMB_WRHR(win)) << 16) << 16);