sys/arch/evbmips/loongson/dev/gcscpcib_pci.c

101

return rdmsr(msr);

sys/arch/evbmips/loongson/dev/glx.c

133

msr = rdmsr(GCSC_DIVIL_BALL_OPTS); /* 0x71 */

sys/arch/evbmips/loongson/dev/glx.c

171

DPRINTF(("IO space 0x%" PRIx64 "\n", rdmsr(0x80000014)));

sys/arch/evbmips/loongson/dev/glx.c

316

msr = rdmsr(GCSC_GLPCI_GLD_MSR_ERROR);

sys/arch/evbmips/loongson/dev/glx.c

372

msr = rdmsr(GCSC_DIVIL_LBAR_SMB);

sys/arch/evbmips/loongson/dev/glx.c

377

msr = rdmsr(GCSC_GLCP_CHIP_REV_ID);

sys/arch/evbmips/loongson/dev/glx.c

383

msr = rdmsr(GCSC_GLPCI_CTRL);

sys/arch/evbmips/loongson/dev/glx.c

403

data = (pcireg_t)rdmsr(pcib_bar_msr[index]);

sys/arch/evbmips/loongson/dev/glx.c

432

msr = rdmsr(pcib_bar_msr[index]);

sys/arch/evbmips/loongson/dev/glx.c

440

msr = rdmsr(GCSC_GLPCI_GLD_MSR_ERROR);

sys/arch/evbmips/loongson/dev/glx.c

448

msr = rdmsr(GCSC_GLPCI_CTRL);

sys/arch/evbmips/loongson/dev/glx.c

498

msr = rdmsr(GCSC_GLIU_PAE);

sys/arch/evbmips/loongson/dev/glx.c

503

msr = rdmsr(GCSC_IDE_GLD_MSR_CAP);

sys/arch/evbmips/loongson/dev/glx.c

510

msr = rdmsr(GCSC_GLPCI_CTRL);

sys/arch/evbmips/loongson/dev/glx.c

520

msr = rdmsr(GCSC_IDE_IO_BAR);

sys/arch/evbmips/loongson/dev/glx.c

535

data = rdmsr(GCSC_IDE_CFG);

sys/arch/evbmips/loongson/dev/glx.c

538

data = rdmsr(GCSC_IDE_DTC);

sys/arch/evbmips/loongson/dev/glx.c

541

data = rdmsr(GCSC_IDE_ETC);

sys/arch/evbmips/loongson/dev/glx.c

559

msr = rdmsr(GCSC_GLIU_PAE);

sys/arch/evbmips/loongson/dev/glx.c

567

msr = rdmsr(GCSC_GLPCI_CTRL);

sys/arch/evbmips/loongson/dev/glx.c

624

msr = rdmsr(GCSC_GLIU_PAE);

sys/arch/evbmips/loongson/dev/glx.c

629

msr = rdmsr(GCSC_ACC_GLD_MSR_CAP);

sys/arch/evbmips/loongson/dev/glx.c

635

msr = rdmsr(GCSC_GLPCI_CTRL);

sys/arch/evbmips/loongson/dev/glx.c

645

msr = rdmsr(GCSC_GLIU_IOD_BM1);

sys/arch/evbmips/loongson/dev/glx.c

671

msr = rdmsr(GCSC_GLIU_PAE);

sys/arch/evbmips/loongson/dev/glx.c

679

msr = rdmsr(GCSC_GLPCI_CTRL);

sys/arch/evbmips/loongson/dev/glx.c

689

msr = rdmsr(GCSC_GLIU_IOD_BM1);

sys/arch/evbmips/loongson/dev/glx.c

724

msr = rdmsr(GCSC_USB_MSR_OHCB);

sys/arch/evbmips/loongson/dev/glx.c

731

msr = rdmsr(GCSC_USB_GLD_MSR_CAP);

sys/arch/evbmips/loongson/dev/glx.c

738

msr = rdmsr(GCSC_GLPCI_CTRL);

sys/arch/evbmips/loongson/dev/glx.c

748

msr = rdmsr(GCSC_USB_MSR_OHCB);

sys/arch/evbmips/loongson/dev/glx.c

779

msr = rdmsr(GCSC_USB_MSR_OHCB);

sys/arch/evbmips/loongson/dev/glx.c

791

msr = rdmsr(GCSC_GLPCI_CTRL);

sys/arch/evbmips/loongson/dev/glx.c

801

msr = rdmsr(GCSC_GLIU_P2D_BM3);

sys/arch/evbmips/loongson/dev/glx.c

808

msr = rdmsr(GCSC_USB_MSR_OHCB);

sys/arch/evbmips/loongson/dev/glx.c

812

msr = rdmsr(GCSC_USB_MSR_OHCB);

sys/arch/evbmips/loongson/dev/glx.c

844

msr = rdmsr(GCSC_USB_MSR_EHCB);

sys/arch/evbmips/loongson/dev/glx.c

851

msr = rdmsr(GCSC_USB_GLD_MSR_CAP);

sys/arch/evbmips/loongson/dev/glx.c

858

msr = rdmsr(GCSC_GLPCI_CTRL);

sys/arch/evbmips/loongson/dev/glx.c

868

msr = rdmsr(GCSC_USB_MSR_EHCB);

sys/arch/evbmips/loongson/dev/glx.c

885

msr = rdmsr(GCSC_USB_MSR_EHCB);

sys/arch/evbmips/loongson/dev/glx.c

904

msr = rdmsr(GCSC_USB_MSR_EHCB);

sys/arch/evbmips/loongson/dev/glx.c

916

msr = rdmsr(GCSC_GLPCI_CTRL);

sys/arch/evbmips/loongson/dev/glx.c

926

msr = rdmsr(GCSC_GLIU_P2D_BM4);

sys/arch/evbmips/loongson/dev/glx.c

933

msr = rdmsr(GCSC_USB_MSR_EHCB);

sys/arch/evbmips/loongson/dev/glx.c

937

msr = rdmsr(GCSC_USB_MSR_EHCB);

sys/arch/evbmips/loongson/dev/glxvar.h

21

uint64_t rdmsr(uint);

sys/arch/evbmips/loongson/yeeloong_machdep.c

279

DPRINTF((" 0x%x", (uint32_t)(rdmsr(GCSC_PIC_SHDW) & 0xff)));

sys/arch/evbmips/loongson/yeeloong_machdep.c

511

gpiobase = BONITO_PCIIO_BASE + (rdmsr(GCSC_DIVIL_LBAR_GPIO) & 0xff00);

sys/arch/evbmips/loongson/yeeloong_machdep.c

530

wrmsr(GCSC_GLCP_SYS_RST, rdmsr(GCSC_GLCP_SYS_RST) | 1);

sys/arch/i386/i386/longrun.c

138

msrinfo.msr = rdmsr(MSR_TMx86_LONGRUN);

sys/arch/i386/i386/longrun.c

141

flags = rdmsr(MSR_TMx86_LONGRUN_FLAGS) & 0x01;

sys/arch/i386/i386/longrun.c

186

msrinfo.msr = rdmsr(MSR_TMx86_LONGRUN);

sys/arch/i386/i386/longrun.c

194

msrinfo.msr = rdmsr(MSR_TMx86_LONGRUN_FLAGS);

sys/arch/i386/i386/mtrr_k6.c

141

uwccr = rdmsr(MSR_K6_UWCCR);

sys/arch/i386/i386/mtrr_k6.c

90

uwccr = rdmsr(MSR_K6_UWCCR);

sys/arch/i386/pci/gcscehci.c

116

ehcibase = rdmsr(GCSCUSB_MSR_EHCB) & 0xffffff00;

sys/arch/i386/pci/gcscide.c

205

reg = rdmsr(drive ? GCSCIDE_ATAC_CH0D1_DMA :

sys/arch/i386/pci/gcscpcib_pci.c

101

return rdmsr(msr);

sys/arch/i386/pci/glxsb.c

214

msr = rdmsr(SB_GLD_MSR_CAP);

sys/arch/i386/pci/glxsb.c

241

msr = rdmsr(SB_GLD_MSR_CTRL);

sys/arch/x86/acpi/acpi_cpu_md.c

342

val = rdmsr(MSR_CMPHALT);

sys/arch/x86/acpi/acpi_cpu_md.c

451

val = rdmsr(MSR_MISC_ENABLE);

sys/arch/x86/acpi/acpi_cpu_md.c

457

val = rdmsr(MSR_MISC_ENABLE);

sys/arch/x86/acpi/acpi_cpu_md.c

643

sc->sc_pstate_aperf = rdmsr(MSR_APERF);

sys/arch/x86/acpi/acpi_cpu_md.c

644

sc->sc_pstate_mperf = rdmsr(MSR_MPERF);

sys/arch/x86/acpi/acpi_cpu_md.c

706

val = rdmsr(ps->ps_status_addr);

sys/arch/x86/acpi/acpi_cpu_md.c

760

val = rdmsr(ps->ps_control_addr);

sys/arch/x86/acpi/acpi_cpu_md.c

914

val = rdmsr(MSR_0FH_STATUS);

sys/arch/x86/acpi/acpi_cpu_md.c

952

val = rdmsr(MSR_THERM_CONTROL);

sys/arch/x86/acpi/acpi_cpu_md.c

988

val = rdmsr(MSR_THERM_CONTROL);

sys/arch/x86/include/cpu_msr.h

53

msr = rdmsr(msrdat->msr_type);

sys/arch/x86/x86/coretemp.c

171

msr = rdmsr(MSR_THERM_STATUS);

sys/arch/x86/x86/coretemp.c

238

msr = rdmsr(MSR_THERM_STATUS);

sys/arch/x86/x86/coretemp.c

252

msr = rdmsr(MSR_BIOS_SIGN);

sys/arch/x86/x86/coretemp.c

365

msr = rdmsr(MSR_THERM_STATUS);

sys/arch/x86/x86/cpu.c

1315

wrmsr(MSR_EFER, rdmsr(MSR_EFER) | EFER_NXE);

sys/arch/x86/x86/cpu_topology.c

175

const uint64_t reg = rdmsr(MSR_NB_CFG);

sys/arch/x86/x86/cpu_ucode_amd.c

117

data->version = rdmsr(MSR_UCODE_AMD_PATCHLEVEL);

sys/arch/x86/x86/cpu_ucode_amd.c

185

patchlevel = rdmsr(MSR_UCODE_AMD_PATCHLEVEL);

sys/arch/x86/x86/cpu_ucode_amd.c

193

if (patchlevel == rdmsr(MSR_UCODE_AMD_PATCHLEVEL)) {

sys/arch/x86/x86/cpu_ucode_intel.c

60

msr = rdmsr(MSR_BIOS_SIGN);

sys/arch/x86/x86/cpu_ucode_intel.c

65

msr = rdmsr(MSR_IA32_PLATFORM_ID);

sys/arch/x86/x86/est.c

1127

msr = rdmsr(MSR_PERF_STATUS);

sys/arch/x86/x86/est.c

1159

msr = rdmsr(MSR_PERF_STATUS);

sys/arch/x86/x86/est.c

1382

fq = oldfq = MSR2MHZ(rdmsr(MSR_PERF_CTL), sc->sc_bus_clock);

sys/arch/x86/x86/est.c

1386

fq = MSR2MHZ(rdmsr(MSR_PERF_STATUS), sc->sc_bus_clock);

sys/arch/x86/x86/hyperv.c

163

return (u_int)rdmsr(MSR_HV_TIME_REF_COUNT);

sys/arch/x86/x86/hyperv.c

170

return rdmsr(MSR_HV_TIME_REF_COUNT);

sys/arch/x86/x86/hyperv.c

228

return rdmsr(MSR_HV_TIME_REF_COUNT);

sys/arch/x86/x86/hyperv.c

265

orig_msr = rdmsr(MSR_HV_REFERENCE_TSC);

sys/arch/x86/x86/hyperv.c

315

last = (u_int)rdmsr(MSR_HV_TIME_REF_COUNT);

sys/arch/x86/x86/hyperv.c

318

u = (u_int)rdmsr(MSR_HV_TIME_REF_COUNT);

sys/arch/x86/x86/hyperv.c

495

hyperv_vcpuid[0] = rdmsr(MSR_HV_VP_INDEX);

sys/arch/x86/x86/hyperv.c

514

hyperv_vcpuid[ci->ci_index] = rdmsr(MSR_HV_VP_INDEX);

sys/arch/x86/x86/hyperv.c

560

lapic_per_second = rdmsr(MSR_HV_APIC_FREQUENCY);

sys/arch/x86/x86/hyperv.c

605

if (rdmsr(MSR_HV_GUEST_OS_ID) == 0) {

sys/arch/x86/x86/hyperv.c

626

hc = rdmsr(MSR_HV_HYPERCALL);

sys/arch/x86/x86/hyperv.c

703

hc_orig = rdmsr(MSR_HV_HYPERCALL);

sys/arch/x86/x86/hyperv.c

718

hc = rdmsr(MSR_HV_HYPERCALL);

sys/arch/x86/x86/hyperv.c

840

orig = rdmsr(MSR_HV_SIMP);

sys/arch/x86/x86/hyperv.c

848

orig = rdmsr(MSR_HV_SIEFP);

sys/arch/x86/x86/hyperv.c

857

orig = rdmsr(sint);

sys/arch/x86/x86/hyperv.c

866

orig = rdmsr(sint);

sys/arch/x86/x86/hyperv.c

874

orig = rdmsr(MSR_HV_SCONTROL);

sys/arch/x86/x86/hyperv.c

888

orig = rdmsr(MSR_HV_SCONTROL);

sys/arch/x86/x86/hyperv.c

895

orig = rdmsr(sint);

sys/arch/x86/x86/hyperv.c

902

orig = rdmsr(sint);

sys/arch/x86/x86/hyperv.c

908

orig = rdmsr(MSR_HV_SIMP);

sys/arch/x86/x86/hyperv.c

914

orig = rdmsr(MSR_HV_SIEFP);

sys/arch/x86/x86/identcpu.c

1002

(rdmsr(MSR_MISC_ENABLE) & (1 << 3)) == 0) {

sys/arch/x86/x86/identcpu.c

1004

wrmsr(MSR_MISC_ENABLE, rdmsr(MSR_MISC_ENABLE) | (1<<3));

sys/arch/x86/x86/identcpu.c

1089

val = rdmsr(MSR_VMCR);

sys/arch/x86/x86/identcpu.c

172

rdmsr(MSR_MISC_ENABLE) & ~IA32_MISC_MWAIT_EN);

sys/arch/x86/x86/identcpu.c

350

val = rdmsr(MSR_BU_CFG2);

sys/arch/x86/x86/identcpu.c

515

wrmsr(MSR_VIA_FCR, rdmsr(MSR_VIA_FCR) | VIA_FCR_CX8_REPORT);

sys/arch/x86/x86/identcpu.c

546

msr = rdmsr(MSR_VIA_FCR);

sys/arch/x86/x86/identcpu.c

611

msr = rdmsr(MSR_VIA_RNG);

sys/arch/x86/x86/identcpu.c

621

msr = rdmsr(MSR_VIA_FCR);

sys/arch/x86/x86/intel_busclock.c

189

msr = rdmsr(MSR_EBL_CR_POWERON);

sys/arch/x86/x86/intel_busclock.c

323

aprint_debug(" (0x%" PRIu64 ")\n", rdmsr(MSR_EBL_CR_POWERON));

sys/arch/x86/x86/intel_busclock.c

336

msr = rdmsr(MSR_EBC_FREQUENCY_ID);

sys/arch/x86/x86/intel_busclock.c

53

msr = rdmsr(MSR_EBL_CR_POWERON);

sys/arch/x86/x86/intel_busclock.c

81

msr = rdmsr(MSR_PERF_STATUS);

sys/arch/x86/x86/lapic.c

159

return rdmsr(MSR_X2APIC_BASE + (reg >> 4));

sys/arch/x86/x86/lapic.c

231

apicbase = rdmsr(MSR_APICBASE);

sys/arch/x86/x86/lapic.c

380

lapic_base = (paddr_t)rdmsr(MSR_APICBASE);

sys/arch/x86/x86/mtrr_i686.c

149

(unsigned long long)rdmsr(mtrr_raw[i].msraddr));

sys/arch/x86/x86/mtrr_i686.c

233

wrmsr(MSR_MTRRdefType, rdmsr(MSR_MTRRdefType) & ~MTRR_I686_ENABLE_MASK);

sys/arch/x86/x86/mtrr_i686.c

256

wrmsr(MSR_MTRRdefType, rdmsr(MSR_MTRRdefType) | MTRR_I686_ENABLE_MASK);

sys/arch/x86/x86/mtrr_i686.c

309

i686_mtrr_cap = rdmsr(MSR_MTRRcap);

sys/arch/x86/x86/mtrr_i686.c

324

mtrr_raw[i].msrval = rdmsr(mtrr_raw[i].msraddr);

sys/arch/x86/x86/odcm.c

333

msr = rdmsr(MSR_THERM_CONTROL);

sys/arch/x86/x86/powernow.c

389

status = rdmsr(MSR_AMDK7_FIDVID_STATUS);

sys/arch/x86/x86/powernow.c

545

status = rdmsr(MSR_AMDK7_FIDVID_STATUS);

sys/arch/x86/x86/powernow.c

555

ctl = rdmsr(MSR_AMDK7_FIDVID_CTL) & PN7_CTR_FIDCHRATIO;

sys/arch/x86/x86/powernow.c

582

status = rdmsr(MSR_AMDK7_FIDVID_STATUS);

sys/arch/x86/x86/powernow.c

667

status = rdmsr(MSR_AMDK7_FIDVID_STATUS);

sys/arch/x86/x86/powernow.c

798

status = rdmsr(MSR_AMDK7_FIDVID_STATUS);

sys/arch/x86/x86/powernow.c

915

status = rdmsr(MSR_AMDK7_FIDVID_STATUS);

sys/arch/x86/x86/spectre.c

131

msr = rdmsr(MSR_IA32_ARCH_CAPABILITIES);

sys/arch/x86/x86/spectre.c

259

msr = rdmsr(MSR_IA32_SPEC_CTRL);

sys/arch/x86/x86/spectre.c

268

msr = rdmsr(MSR_IC_CFG);

sys/arch/x86/x86/spectre.c

413

msr = rdmsr(MSR_IA32_ARCH_CAPABILITIES);

sys/arch/x86/x86/spectre.c

485

msr = rdmsr(msrval);

sys/arch/x86/x86/spectre.c

684

msr = rdmsr(MSR_IA32_ARCH_CAPABILITIES);

sys/arch/x86/x86/spectre.c

802

msr = rdmsr(MSR_IA32_TSX_CTRL);

sys/arch/x86/x86/spectre.c

854

msr = rdmsr(MSR_IA32_ARCH_CAPABILITIES);

sys/arch/x86/x86/svs.c

745

msr = rdmsr(MSR_IA32_ARCH_CAPABILITIES);

sys/arch/xen/x86/cpu.c

1075

wrmsr(MSR_EFER, rdmsr(MSR_EFER) | EFER_NXE);

sys/dev/nvmm/x86/nvmm_x86.h

100

struct nvmm_x86_exit_rdmsr rdmsr;

sys/dev/nvmm/x86/nvmm_x86_svm.c

1256

if (exit->u.rdmsr.msr == MSR_EFER) {

sys/dev/nvmm/x86/nvmm_x86_svm.c

1262

if (exit->u.rdmsr.msr == MSR_NB_CFG) {

sys/dev/nvmm/x86/nvmm_x86_svm.c

1269

if (msr_ignore_list[i] != exit->u.rdmsr.msr)

sys/dev/nvmm/x86/nvmm_x86_svm.c

1319

exit->u.rdmsr.msr = (cpudata->gprs[NVMM_X64_GPR_RCX] & 0xFFFFFFFF);

sys/dev/nvmm/x86/nvmm_x86_svm.c

1320

exit->u.rdmsr.npc = cpudata->vmcb->ctrl.nrip;

sys/dev/nvmm/x86/nvmm_x86_svm.c

1627

cpudata->fsbase = rdmsr(MSR_FSBASE);

sys/dev/nvmm/x86/nvmm_x86_svm.c

1628

cpudata->kernelgsbase = rdmsr(MSR_KERNELGSBASE);

sys/dev/nvmm/x86/nvmm_x86_svm.c

2461

cpudata->star = rdmsr(MSR_STAR);

sys/dev/nvmm/x86/nvmm_x86_svm.c

2462

cpudata->lstar = rdmsr(MSR_LSTAR);

sys/dev/nvmm/x86/nvmm_x86_svm.c

2463

cpudata->cstar = rdmsr(MSR_CSTAR);

sys/dev/nvmm/x86/nvmm_x86_svm.c

2464

cpudata->sfmask = rdmsr(MSR_SFMASK);

sys/dev/nvmm/x86/nvmm_x86_svm.c

2761

msr = rdmsr(MSR_VMCR);

sys/dev/nvmm/x86/nvmm_x86_svm.c

2799

msr = rdmsr(MSR_VMCR);

sys/dev/nvmm/x86/nvmm_x86_svm.c

2808

msr = rdmsr(MSR_EFER);

sys/dev/nvmm/x86/nvmm_x86_vmx.c

1899

if (exit->u.rdmsr.msr == MSR_CR_PAT) {

sys/dev/nvmm/x86/nvmm_x86_vmx.c

1905

if (exit->u.rdmsr.msr == MSR_MISC_ENABLE) {

sys/dev/nvmm/x86/nvmm_x86_vmx.c

1911

if (exit->u.rdmsr.msr == MSR_IA32_ARCH_CAPABILITIES) {

sys/dev/nvmm/x86/nvmm_x86_vmx.c

1920

val = rdmsr(MSR_IA32_ARCH_CAPABILITIES);

sys/dev/nvmm/x86/nvmm_x86_vmx.c

1930

if (msr_ignore_list[i] != exit->u.rdmsr.msr)

sys/dev/nvmm/x86/nvmm_x86_vmx.c

1981

exit->u.rdmsr.msr = (cpudata->gprs[NVMM_X64_GPR_RCX] & 0xFFFFFFFF);

sys/dev/nvmm/x86/nvmm_x86_vmx.c

1990

exit->u.rdmsr.npc = rip + inslen;

sys/dev/nvmm/x86/nvmm_x86_vmx.c

2280

vmx_vmwrite(VMCS_HOST_FS_BASE, rdmsr(MSR_FSBASE));

sys/dev/nvmm/x86/nvmm_x86_vmx.c

2284

cpudata->kernelgsbase = rdmsr(MSR_KERNELGSBASE);

sys/dev/nvmm/x86/nvmm_x86_vmx.c

2425

vmx_vmwrite(VMCS_HOST_GS_BASE, rdmsr(MSR_GSBASE));

sys/dev/nvmm/x86/nvmm_x86_vmx.c

3158

vmx_vmwrite(VMCS_HOST_IA32_PAT, rdmsr(MSR_CR_PAT));

sys/dev/nvmm/x86/nvmm_x86_vmx.c

3159

vmx_vmwrite(VMCS_HOST_IA32_EFER, rdmsr(MSR_EFER));

sys/dev/nvmm/x86/nvmm_x86_vmx.c

3174

cpudata->gmsr_misc_enable = rdmsr(MSR_MISC_ENABLE);

sys/dev/nvmm/x86/nvmm_x86_vmx.c

3189

cpudata->star = rdmsr(MSR_STAR);

sys/dev/nvmm/x86/nvmm_x86_vmx.c

3190

cpudata->lstar = rdmsr(MSR_LSTAR);

sys/dev/nvmm/x86/nvmm_x86_vmx.c

3191

cpudata->cstar = rdmsr(MSR_CSTAR);

sys/dev/nvmm/x86/nvmm_x86_vmx.c

3192

cpudata->sfmask = rdmsr(MSR_SFMASK);

sys/dev/nvmm/x86/nvmm_x86_vmx.c

3518

basic = rdmsr(MSR_IA32_VMX_BASIC);

sys/dev/nvmm/x86/nvmm_x86_vmx.c

3521

val = rdmsr(msr_ctls);

sys/dev/nvmm/x86/nvmm_x86_vmx.c

3523

true_val = rdmsr(msr_true_ctls);

sys/dev/nvmm/x86/nvmm_x86_vmx.c

3548

basic = rdmsr(MSR_IA32_VMX_BASIC);

sys/dev/nvmm/x86/nvmm_x86_vmx.c

3551

val = rdmsr(msr_ctls);

sys/dev/nvmm/x86/nvmm_x86_vmx.c

3553

true_val = rdmsr(msr_true_ctls);

sys/dev/nvmm/x86/nvmm_x86_vmx.c

3600

msr = rdmsr(MSR_IA32_FEATURE_CONTROL);

sys/dev/nvmm/x86/nvmm_x86_vmx.c

3607

msr = rdmsr(MSR_IA32_VMX_BASIC);

sys/dev/nvmm/x86/nvmm_x86_vmx.c

3618

vmx_cr0_fixed0 = rdmsr(MSR_IA32_VMX_CR0_FIXED0) & ~(CR0_PG|CR0_PE);

sys/dev/nvmm/x86/nvmm_x86_vmx.c

3619

vmx_cr0_fixed1 = rdmsr(MSR_IA32_VMX_CR0_FIXED1) | (CR0_PG|CR0_PE);

sys/dev/nvmm/x86/nvmm_x86_vmx.c

3626

vmx_cr4_fixed0 = rdmsr(MSR_IA32_VMX_CR4_FIXED0);

sys/dev/nvmm/x86/nvmm_x86_vmx.c

3627

vmx_cr4_fixed1 = rdmsr(MSR_IA32_VMX_CR4_FIXED1);

sys/dev/nvmm/x86/nvmm_x86_vmx.c

3682

msr = rdmsr(MSR_IA32_VMX_EPT_VPID_CAP);

sys/dev/nvmm/x86/nvmm_x86_vmx.c

3731

msr = rdmsr(MSR_IA32_FEATURE_CONTROL);

sys/dev/nvmm/x86/nvmm_x86_vmx.c

3770

msr = rdmsr(MSR_IA32_ARCH_CAPABILITIES);

sys/dev/nvmm/x86/nvmm_x86_vmx.c

3857

msr = rdmsr(MSR_IA32_VMX_EPT_VPID_CAP);

sys/dev/nvmm/x86/nvmm_x86_vmx.c

916

msr = rdmsr(MSR_IA32_VMX_BASIC);

sys/dev/pci/agp_nvidia.c

370

base = rdmsr(IORR_BASE0 + 2 * iorr_addr);

sys/dev/pci/agp_nvidia.c

371

mask = rdmsr(IORR_MASK0 + 2 * iorr_addr);

sys/dev/pci/agp_nvidia.c

391

sys = rdmsr(SYSCFG);

sys/dev/tprof/tprof_x86_amd.c

135

return rdmsr(PERFCTR(counter));

sys/dev/tprof/tprof_x86_amd.c

169

wrmsr(PERFEVTSEL(bit), rdmsr(PERFEVTSEL(bit)) | PESR_EN);

sys/dev/tprof/tprof_x86_amd.c

181

wrmsr(PERFEVTSEL(bit), rdmsr(PERFEVTSEL(bit)) & ~PESR_EN);

sys/dev/tprof/tprof_x86_intel.c

132

return rdmsr(PERFCTR(counter));

sys/dev/tprof/tprof_x86_intel.c

160

wrmsr(PERFEVTSEL(bit), rdmsr(PERFEVTSEL(bit)) | PERFEVTSEL_EN);

sys/dev/tprof/tprof_x86_intel.c

172

wrmsr(PERFEVTSEL(bit), rdmsr(PERFEVTSEL(bit)) &

usr.sbin/cpuctl/arch/i386.c

1914

const uint64_t reg = rdmsr(MSR_NB_CFG);