radeonfb_put32
radeonfb_put32(sc, RADEON_SEPROM_CNTL1,
radeonfb_put32(sc, RADEON_VIPH_CONTROL, viphctl & ~RADEON_VIPH_EN);
radeonfb_put32(sc, RADEON_BUS_CNTL, busctl & ~RADEON_BUS_BIOS_DIS_ROM);
radeonfb_put32(sc, RADEON_CRTC_GEN_CNTL, ((crtcg & ~RADEON_CRTC_EN) |
radeonfb_put32(sc, RADEON_CRTC2_GEN_CNTL,
radeonfb_put32(sc, RADEON_CRTC_EXT_CNTL, (extc & ~RADEON_CRTC_CRT_ON) |
radeonfb_put32(sc, RADEON_CRTC_EXT_CNTL, extc);
radeonfb_put32(sc, RADEON_CRTC2_GEN_CNTL, crtc2g);
radeonfb_put32(sc, RADEON_CRTC_GEN_CNTL, crtcg);
radeonfb_put32(sc, RADEON_BUS_CNTL, busctl);
radeonfb_put32(sc, RADEON_VIPH_CONTROL, viphctl);
radeonfb_put32(sc, RADEON_SEPROM_CNTL1, seprom);
radeonfb_put32(sc, reg, val);
radeonfb_put32(sc, RADEON_MM_INDEX, idx);
radeonfb_put32(sc, RADEON_MM_INDEX, idx);
radeonfb_put32(sc, RADEON_MM_DATA, val);
radeonfb_put32(sc, RADEON_MM_INDEX, idx);
radeonfb_put32(sc, RADEON_MM_DATA, val);
radeonfb_put32(sc, RADEON_CLOCK_CNTL_INDEX, (idx & 0x3f));
radeonfb_put32(sc, RADEON_CLOCK_CNTL_INDEX, (idx & 0x3f) |
radeonfb_put32(sc, RADEON_CLOCK_CNTL_DATA, val);
radeonfb_put32(sc, RADEON_CLOCK_CNTL_INDEX, 0);
radeonfb_put32(sc, RADEON_CLOCK_CNTL_INDEX, (idx & 0x3f) |
radeonfb_put32(sc, RADEON_CLOCK_CNTL_DATA, val);
radeonfb_put32(sc, RADEON_CLOCK_CNTL_INDEX, 0);
radeonfb_put32(sc, RADEON_LVDS_GEN_CNTL, lvds);
radeonfb_put32(sc, RADEON_LVDS_GEN_CNTL, lvds);
radeonfb_put32(sc, index, GETBIOS32(sc, offset));
#define PUT32(sc, r, v) radeonfb_put32(sc, r, v)
void radeonfb_put32(struct radeonfb_softc *, uint32_t, uint32_t);