psc_reg2
psc_reg2(PSC_CTLBASE + (i << 4)) = 0x1000;
psc_reg2(PSC_CMDBASE + (i << 5)) = 0x1100;
psc_reg2(PSC_CMDBASE + (i << 5) + PSC_SET1) = 0x1100;
*rset = (psc_reg2(chan_ctrl) & 1) << 4;
(void)psc_reg2(rset_cmd);
psc_reg2(rset_cmd) = 0x8200;
psc_reg2(rset_cmd) = 0x200;
psc_reg2(rset_cmd) = 0x100;
psc_reg2(rset_cmd) = 0x8800;
psc_reg2(chan_ctrl) = 0x400;
psc_reg2(chan_ctrl) = 0x8400;
while (!(psc_reg2(chan_ctrl) & 0x4000))
while (!(psc_reg2(rset_cmd) & 0x100))
while (psc_reg2(rset_cmd) & 0x800)
if (psc_reg2(rset_cmd) & 0x400) {
psc_reg2(chan_ctrl) = 0x8200;
while (psc_reg2(chan_ctrl) & 0x200)
if (psc_reg2(rset_cmd) & 0x400) {
psc_reg2(chan_ctrl) = 0x8800;
psc_reg2(PSC_CTLBASE + (i << 4)) = 0x8800;
psc_reg2(PSC_ENETRD_CTL) = 0x8800;
psc_reg2(PSC_ENETRD_CTL) = 0x1000;
psc_reg2(PSC_ENETRD_CMD + PSC_SET0) = 0x1100;
psc_reg2(PSC_ENETRD_CMD + PSC_SET1) = 0x1100;
psc_reg2(PSC_ENETWR_CTL) = 0x8800;
psc_reg2(PSC_ENETWR_CTL) = 0x1000;
psc_reg2(PSC_ENETWR_CMD + PSC_SET0) = 0x1100;
psc_reg2(PSC_ENETWR_CMD + PSC_SET1) = 0x1100;
psc_reg2(PSC_ENETWR_CTL) = 0x9000;
psc_reg2(PSC_ENETRD_CTL) = 0x9000;
psc_reg2(PSC_ENETWR_CTL) = 0x0400;
psc_reg2(PSC_ENETRD_CTL) = 0x0400;
psc_reg2(PSC_ENETWR_CMD + sc->sc_txset) = 0x9800;
status = psc_reg2(PSC_ENETRD_CTL);
psc_reg2(PSC_ENETRD_CMD + sc->sc_rxset) = 0x1100;
psc_reg2(PSC_ENETRD_CMD + sc->sc_rxset) = 0x9000;
psc_reg2(PSC_ENETRD_CMD + sc->sc_rxset) = 0x9800;
status = psc_reg2(PSC_ENETWR_CTL);
psc_reg2(PSC_ENETWR_CMD + sc->sc_txseti) = 0x100;
psc_reg2(PSC_ENETRD_CTL) = 0x8800;
psc_reg2(PSC_ENETRD_CTL) = 0x400;
psc_reg2(PSC_ENETRD_CTL) = 0x8800;
psc_reg2(PSC_ENETRD_CTL) = 0x400;
psc_reg2(PSC_ENETRD_CMD + PSC_SET0) = 0x9800;
psc_reg2(PSC_ENETRD_CMD + PSC_SET1) = 0x9800;
psc_reg2(PSC_ENETRD_CMD + set) = 0x0100;
psc_reg2(PSC_ENETRD_CMD + set) = 0x9800;
psc_reg2(PSC_ENETWR_CTL) = 0x8800;
psc_reg2(PSC_ENETWR_CTL) = 0x400;