psc_reg1
psc_reg1(PSC_ISR_BASE + 0x10 * i) = 0x0F;
psc_reg1(PSC_IER_BASE + 0x10 * i) = 0x0F;
psc_reg1(PSC_LEV4_IER) = 0x86; /* enable SCC */
while ((intbits = psc_reg1(PSC_LEV3_ISR)) != psc_reg1(PSC_LEV3_ISR))
intbits &= 0x1 & psc_reg1(PSC_LEV3_IER);
while ((intbits = psc_reg1(PSC_LEV4_ISR)) != psc_reg1(PSC_LEV4_ISR))
intbits &= 0xf & psc_reg1(PSC_LEV4_IER);
while ((intbits = psc_reg1(PSC_LEV5_ISR)) != psc_reg1(PSC_LEV5_ISR))
intbits &= 0x3 & psc_reg1(PSC_LEV5_IER);
while ((intbits = psc_reg1(PSC_LEV6_ISR)) != psc_reg1(PSC_LEV6_ISR))
intbits &= 0x7 & psc_reg1(PSC_LEV6_IER);
psc_reg1(PSC_LEV4_IER) = 0x80 | (1 << PSCINTR_ENET_DMA);
psc_reg1(PSC_LEV3_IER) = 0x80 | (1 << PSCINTR_ENET);
psc_reg1(PSC_LEV4_IER) = (1 << PSCINTR_ENET_DMA);
psc_reg1(PSC_LEV3_IER) = (1 << PSCINTR_ENET);