sys/arch/evbarm/stand/boot2440/dm9000.c
308
CSR_WRITE_2(l, MWCMD, val);
sys/arch/sandpoint/stand/altboot/fxp.c
418
CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg);
sys/arch/sandpoint/stand/altboot/fxp.c
420
CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL,
sys/arch/sandpoint/stand/altboot/fxp.c
423
CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg);
sys/arch/sandpoint/stand/altboot/fxp.c
433
CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS);
sys/arch/sandpoint/stand/altboot/fxp.c
444
CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS);
sys/arch/sandpoint/stand/altboot/fxp.c
446
CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL,
sys/arch/sandpoint/stand/altboot/fxp.c
453
CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS);
sys/arch/sandpoint/stand/altboot/fxp.c
456
CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0);
sys/arch/sandpoint/stand/altboot/fxp.c
470
CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS);
sys/arch/sandpoint/stand/altboot/fxp.c
484
CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL,
sys/arch/sandpoint/stand/altboot/fxp.c
490
CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg);
sys/arch/sandpoint/stand/altboot/fxp.c
493
CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0);
sys/arch/sandpoint/stand/altboot/kse.c
151
CSR_WRITE_2(l, CIDR, 1);
sys/arch/sandpoint/stand/altboot/kse.c
264
CSR_WRITE_2(l, P1CR4, val);
sys/arch/sandpoint/stand/altboot/nvt.c
232
CSR_WRITE_2(l, VR_ISR, ~0);
sys/arch/sandpoint/stand/altboot/nvt.c
233
CSR_WRITE_2(l, VR_IEN, 0);
sys/arch/sandpoint/stand/altboot/nvt.c
366
CSR_WRITE_2(l, VR_MIIDATA, data);
sys/arch/sandpoint/stand/altboot/rge.c
220
CSR_WRITE_2(l, RGE_RMS, FRAMESIZE);
sys/arch/sandpoint/stand/altboot/rge.c
227
CSR_WRITE_2(l, RGE_ISR, ~0);
sys/arch/sandpoint/stand/altboot/rge.c
228
CSR_WRITE_2(l, RGE_IMR, 0);
sys/arch/sandpoint/stand/altboot/skg.c
221
CSR_WRITE_2(l, SK_CSR, CSR_SW_RESET);
sys/arch/sandpoint/stand/altboot/skg.c
222
CSR_WRITE_2(l, SK_CSR, CSR_MASTER_RESET);
sys/arch/sandpoint/stand/altboot/skg.c
223
CSR_WRITE_2(l, SK_LINK_CTRL, LINK_RESET_SET);
sys/arch/sandpoint/stand/altboot/skg.c
225
CSR_WRITE_2(l, SK_CSR, CSR_SW_UNRESET);
sys/arch/sandpoint/stand/altboot/skg.c
227
CSR_WRITE_2(l, SK_CSR, CSR_MASTER_UNRESET);
sys/arch/sandpoint/stand/altboot/skg.c
228
CSR_WRITE_2(l, SK_LINK_CTRL, LINK_RESET_CLEAR);
sys/arch/sandpoint/stand/altboot/skg.c
247
CSR_WRITE_2(l, YUKON_SA1 + i * 4,
sys/arch/sandpoint/stand/altboot/skg.c
323
CSR_WRITE_2(l, YUKON_GPCR, reg);
sys/arch/sandpoint/stand/altboot/skg.c
403
CSR_WRITE_2(l, YUKON_SMICR, SMICR_PHYAD(phy) | SMICR_REGAD(reg) |
sys/arch/sandpoint/stand/altboot/skg.c
422
CSR_WRITE_2(l, YUKON_SMIDR, data);
sys/arch/sandpoint/stand/altboot/skg.c
423
CSR_WRITE_2(l, YUKON_SMICR, SMICR_PHYAD(phy) | SMICR_REGAD(reg) |
sys/arch/sandpoint/stand/altboot/stg.c
192
CSR_WRITE_2(l, STGE_EepromCtrl,
sys/arch/sandpoint/stand/altboot/stg.c
231
CSR_WRITE_2(l, STGE_IntEnable, 0);
sys/arch/sandpoint/stand/altboot/stg.c
232
CSR_WRITE_2(l, STGE_ReceiveMode, RM_ReceiveUnicast |
sys/arch/sandpoint/stand/altboot/stg.c
238
CSR_WRITE_2(l, STGE_MaxFrameSize, FRAMESIZE);
sys/arch/sandpoint/stand/altboot/stg.c
244
CSR_WRITE_2(l, STGE_DebugCtrl,
sys/arch/sandpoint/stand/altboot/stg.c
246
CSR_WRITE_2(l, STGE_DebugCtrl,
sys/arch/sandpoint/stand/altboot/stg.c
248
CSR_WRITE_2(l, STGE_DebugCtrl,
sys/arch/sandpoint/stand/altboot/vge.c
294
CSR_WRITE_2(l, VR_RDCSIZE, NRXDESC - 1);
sys/arch/sandpoint/stand/altboot/vge.c
295
CSR_WRITE_2(l, VR_RBRDU, NRXDESC - 1);
sys/arch/sandpoint/stand/altboot/vge.c
297
CSR_WRITE_2(l, VR_TDCSIZE, 0);
sys/arch/sandpoint/stand/altboot/vge.c
302
CSR_WRITE_2(l, VR_TDCSR, 01);
sys/arch/sandpoint/stand/altboot/vge.c
330
CSR_WRITE_2(l, VR_TDCSR, 04);
sys/arch/sandpoint/stand/altboot/vge.c
448
CSR_WRITE_2(l, VR_MIIDATA, data);
sys/dev/ic/an.c
1388
CSR_WRITE_2(sc, AN_EVENT_ACK, AN_EV_RX);
sys/dev/ic/an.c
1412
CSR_WRITE_2(sc, AN_EVENT_ACK, AN_EV_RX);
sys/dev/ic/an.c
1424
CSR_WRITE_2(sc, AN_EVENT_ACK, AN_EV_RX);
sys/dev/ic/an.c
1434
CSR_WRITE_2(sc, AN_EVENT_ACK, AN_EV_RX);
sys/dev/ic/an.c
1442
CSR_WRITE_2(sc, AN_EVENT_ACK, AN_EV_RX);
sys/dev/ic/an.c
1454
CSR_WRITE_2(sc, AN_EVENT_ACK, AN_EV_RX);
sys/dev/ic/an.c
1492
CSR_WRITE_2(sc, AN_EVENT_ACK, AN_EV_RX);
sys/dev/ic/an.c
1545
CSR_WRITE_2(sc, AN_EVENT_ACK, status & (AN_EV_TX | AN_EV_TX_EXC));
sys/dev/ic/an.c
1584
CSR_WRITE_2(sc, AN_EVENT_ACK, AN_EV_LINKSTAT);
sys/dev/ic/an.c
1610
CSR_WRITE_2(sc, AN_EVENT_ACK, AN_EV_CLR_STUCK_BUSY);
sys/dev/ic/an.c
1613
CSR_WRITE_2(sc, AN_PARAM0, val);
sys/dev/ic/an.c
1614
CSR_WRITE_2(sc, AN_PARAM1, 0);
sys/dev/ic/an.c
1615
CSR_WRITE_2(sc, AN_PARAM2, 0);
sys/dev/ic/an.c
1616
CSR_WRITE_2(sc, AN_COMMAND, cmd);
sys/dev/ic/an.c
1633
CSR_WRITE_2(sc, AN_EVENT_ACK, AN_EV_CLR_STUCK_BUSY);
sys/dev/ic/an.c
1636
CSR_WRITE_2(sc, AN_EVENT_ACK, AN_EV_CMD);
sys/dev/ic/an.c
1666
CSR_WRITE_2(sc, AN_COMMAND, AN_CMD_NOOP2);
sys/dev/ic/an.c
1672
CSR_WRITE_2(sc, AN_EVENT_ACK, AN_EV_CMD);
sys/dev/ic/an.c
1680
CSR_WRITE_2(sc, AN_SEL0, id);
sys/dev/ic/an.c
1681
CSR_WRITE_2(sc, AN_OFF0, off);
sys/dev/ic/an.c
1803
CSR_WRITE_2(sc, AN_EVENT_ACK, AN_EV_ALLOC);
sys/dev/ic/an.c
461
CSR_WRITE_2(sc, AN_INT_EN, 0);
sys/dev/ic/an.c
462
CSR_WRITE_2(sc, AN_EVENT_ACK, ~0);
sys/dev/ic/an.c
467
CSR_WRITE_2(sc, AN_INT_EN, 0);
sys/dev/ic/an.c
486
CSR_WRITE_2(sc, AN_EVENT_ACK, ~0);
sys/dev/ic/an.c
501
CSR_WRITE_2(sc, AN_EVENT_ACK, status & ~(AN_INTRS));
sys/dev/ic/an.c
526
CSR_WRITE_2(sc, AN_INT_EN, AN_INTRS);
sys/dev/ic/an.c
550
CSR_WRITE_2(sc, AN_SW0, AN_MAGIC);
sys/dev/ic/an.c
678
CSR_WRITE_2(sc, AN_INT_EN, AN_INTRS);
sys/dev/ic/an.c
697
CSR_WRITE_2(sc, AN_INT_EN, 0);
sys/dev/ic/bwi.c
1256
CSR_WRITE_2(sc, data_reg, v);
sys/dev/ic/bwi.c
1269
CSR_WRITE_2(sc, BWI_MOBJ_DATA_UNALIGN, v >> 16);
sys/dev/ic/bwi.c
1272
CSR_WRITE_2(sc, BWI_MOBJ_DATA, v & 0xffff);
sys/dev/ic/bwi.c
1316
CSR_WRITE_2(mac->mac_sc, BWI_BBP_ATTEN, BWI_BBP_ATTEN_MAGIC);
sys/dev/ic/bwi.c
1397
CSR_WRITE_2(sc, BWI_BBP_ATTEN, 0);
sys/dev/ic/bwi.c
1414
CSR_WRITE_2(sc, 0x60e, 0);
sys/dev/ic/bwi.c
1415
CSR_WRITE_2(sc, 0x610, 0x8000);
sys/dev/ic/bwi.c
1416
CSR_WRITE_2(sc, 0x604, 0);
sys/dev/ic/bwi.c
1417
CSR_WRITE_2(sc, 0x606, 0x200);
sys/dev/ic/bwi.c
1441
CSR_WRITE_2(sc, BWI_MAC_POWERUP_DELAY, sc->sc_pwron_delay);
sys/dev/ic/bwi.c
1490
CSR_WRITE_2(sc, 0x612, 0x50); /* Force Pre-TBTT to 80? */
sys/dev/ic/bwi.c
1526
CSR_WRITE_2(sc, BWI_BBP_ATTEN, 0);
sys/dev/ic/bwi.c
1764
CSR_WRITE_2(sc, 0x568, 0);
sys/dev/ic/bwi.c
1765
CSR_WRITE_2(sc, 0x7c0, 0);
sys/dev/ic/bwi.c
1766
CSR_WRITE_2(sc, 0x50c, val_50c);
sys/dev/ic/bwi.c
1767
CSR_WRITE_2(sc, 0x508, 0);
sys/dev/ic/bwi.c
1768
CSR_WRITE_2(sc, 0x50a, 0);
sys/dev/ic/bwi.c
1769
CSR_WRITE_2(sc, 0x54c, 0);
sys/dev/ic/bwi.c
1770
CSR_WRITE_2(sc, 0x56a, 0x14);
sys/dev/ic/bwi.c
1771
CSR_WRITE_2(sc, 0x568, 0x826);
sys/dev/ic/bwi.c
1772
CSR_WRITE_2(sc, 0x500, 0);
sys/dev/ic/bwi.c
1773
CSR_WRITE_2(sc, 0x502, 0x30);
sys/dev/ic/bwi.c
2272
CSR_WRITE_2(sc, ofs, val16);
sys/dev/ic/bwi.c
2374
CSR_WRITE_2(sc, BWI_MAC_PRE_TBTT, pre_tbtt);
sys/dev/ic/bwi.c
2610
CSR_WRITE_2(sc, BWI_BBP_ATTEN, BWI_BBP_ATTEN_MAGIC);
sys/dev/ic/bwi.c
2687
CSR_WRITE_2(mac->mac_sc, BWI_MAC_SLOTTIME,
sys/dev/ic/bwi.c
3044
CSR_WRITE_2(sc, BWI_PHY_CTRL, ctrl);
sys/dev/ic/bwi.c
3045
CSR_WRITE_2(sc, BWI_PHY_DATA, data);
sys/dev/ic/bwi.c
3054
CSR_WRITE_2(sc, BWI_PHY_CTRL, ctrl);
sys/dev/ic/bwi.c
3349
CSR_WRITE_2(sc, BWI_BPHY_CTRL, BWI_BPHY_CTRL_INIT);
sys/dev/ic/bwi.c
3359
CSR_WRITE_2(sc, BWI_PHY_MAGIC_REG1, BWI_PHY_MAGIC_REG1_VAL1);
sys/dev/ic/bwi.c
3396
CSR_WRITE_2(sc, BWI_RF_CHAN_EX, 0x1100);
sys/dev/ic/bwi.c
3443
CSR_WRITE_2(sc, BWI_RF_ANTDIV, 0);
sys/dev/ic/bwi.c
3466
CSR_WRITE_2(sc, BWI_BPHY_CTRL, BWI_BPHY_CTRL_INIT);
sys/dev/ic/bwi.c
3474
CSR_WRITE_2(sc, BWI_PHY_MAGIC_REG1, BWI_PHY_MAGIC_REG1_VAL1);
sys/dev/ic/bwi.c
3625
CSR_WRITE_2(sc, BWI_PHY_MAGIC_REG1, BWI_PHY_MAGIC_REG1_VAL2);
sys/dev/ic/bwi.c
3632
CSR_WRITE_2(sc, BWI_BBP_ATTEN, BWI_BBP_ATTEN_MAGIC2);
sys/dev/ic/bwi.c
3645
CSR_WRITE_2(sc, BWI_BBP_ATTEN, 0);
sys/dev/ic/bwi.c
3965
CSR_WRITE_2(sc, BWI_RF_CTRL, ctrl);
sys/dev/ic/bwi.c
3966
CSR_WRITE_2(sc, BWI_RF_DATA_LO, data);
sys/dev/ic/bwi.c
3984
CSR_WRITE_2(sc, BWI_RF_CTRL, ctrl);
sys/dev/ic/bwi.c
4015
CSR_WRITE_2(sc, BWI_RF_CTRL, BWI_RF_CTRL_RFINFO);
sys/dev/ic/bwi.c
4019
CSR_WRITE_2(sc, BWI_RF_CTRL, BWI_RF_CTRL_RFINFO);
sys/dev/ic/bwi.c
4118
CSR_WRITE_2(sc, BWI_RF_CHAN, BWI_RF_2GHZ_CHAN(chan));
sys/dev/ic/bwi.c
4343
CSR_WRITE_2(sc, BWI_RF_CHAN, BWI_RF_2GHZ_CHAN(chan + 4));
sys/dev/ic/bwi.c
4345
CSR_WRITE_2(sc, BWI_RF_CHAN, BWI_RF_2GHZ_CHAN(1));
sys/dev/ic/bwi.c
4347
CSR_WRITE_2(sc, BWI_RF_CHAN, BWI_RF_2GHZ_CHAN(chan));
sys/dev/ic/bwi.c
4548
CSR_WRITE_2(sc, BWI_BPHY_CTRL, 0x3f3f);
sys/dev/ic/bwi.c
4585
CSR_WRITE_2(sc, BWI_BBP_ATTEN, 0x122);
sys/dev/ic/bwi.c
4741
CSR_WRITE_2(sc, BWI_BBP_ATTEN, bbp_atten);
sys/dev/ic/bwi.c
4743
CSR_WRITE_2(sc, BWI_RF_CHAN_EX, rf_chan_ex);
sys/dev/ic/bwi.c
4750
CSR_WRITE_2(sc, BWI_BPHY_CTRL, bphy_ctrl);
sys/dev/ic/bwi.c
5057
CSR_WRITE_2(sc, BWI_RF_ANTDIV, ant_div | 0x8000);
sys/dev/ic/bwi.c
5086
CSR_WRITE_2(sc, BWI_RF_CHAN_EX, 0);
sys/dev/ic/bwi.c
5134
CSR_WRITE_2(sc, BWI_RF_CHAN_EX, chan_ex);
sys/dev/ic/bwi.c
5148
CSR_WRITE_2(sc, BWI_RF_ANTDIV, ant_div);
sys/dev/ic/bwi.c
5449
CSR_WRITE_2(sc, BWI_BPHY_CTRL, 0x7f7f);
sys/dev/ic/bwi.c
5463
CSR_WRITE_2(sc, BWI_BBP_ATTEN, 0x40);
sys/dev/ic/bwi.c
5465
CSR_WRITE_2(sc, BWI_BBP_ATTEN, 0x122);
sys/dev/ic/bwi.c
5489
CSR_WRITE_2(sc, BWI_RF_ANTDIV, ant_div);
sys/dev/ic/bwi.c
5497
CSR_WRITE_2(sc, BWI_RF_CHAN_EX, chan_ex);
sys/dev/ic/bwi.c
5824
CSR_WRITE_2(sc, BWI_RF_ANTDIV, ant_div);
sys/dev/ic/bwi.c
5825
CSR_WRITE_2(sc, BWI_BBP_ATTEN, bbp_atten);
sys/dev/ic/bwi.c
5826
CSR_WRITE_2(sc, BWI_RF_CHAN_EX, chan_ex);
sys/dev/ic/bwi.c
6373
CSR_WRITE_2(sc, BWI_PHY_CTRL, 0x3f3f);
sys/dev/ic/bwi.c
6450
CSR_WRITE_2(sc, BWI_BPHY_CTRL, bphy_ctrl);
sys/dev/ic/bwi.c
6756
CSR_WRITE_2(sc, BWI_MAC_GPIO_CTRL, val);
sys/dev/ic/bwi.c
6802
CSR_WRITE_2(sc, BWI_MAC_GPIO_CTRL, val);
sys/dev/ic/bwi.c
6823
CSR_WRITE_2(sc, BWI_MAC_GPIO_CTRL, val);
sys/dev/ic/bwi.c
808
CSR_WRITE_2(sc, BWI_MAC_PS_STATUS, 0x2);
sys/dev/ic/bwi.c
8799
CSR_WRITE_2(sc, BWI_ADDR_FILTER_CTRL,
sys/dev/ic/bwi.c
8807
CSR_WRITE_2(sc, BWI_ADDR_FILTER_DATA, addr_val);
sys/dev/ic/bwivar.h
102
CSR_WRITE_2((sc), (reg), (CSR_READ_2((sc), (reg)) & (filt)) | (bits))
sys/dev/ic/bwivar.h
107
CSR_WRITE_2((sc), (reg), CSR_READ_2((sc), (reg)) & ~(bits))
sys/dev/ic/bwivar.h
97
CSR_WRITE_2((sc), (reg), CSR_READ_2((sc), (reg)) | (bits))
sys/dev/ic/com.c
1945
CSR_WRITE_2(regsp, COM_REG_DLBL, sc->sc_dlbl +
sys/dev/ic/com.c
2796
CSR_WRITE_2(regsp, COM_REG_DLBL, rate);
sys/dev/ic/i82557.c
613
CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg);
sys/dev/ic/i82557.c
615
CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL,
sys/dev/ic/i82557.c
618
CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg);
sys/dev/ic/i82557.c
655
CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS);
sys/dev/ic/i82557.c
666
CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS);
sys/dev/ic/i82557.c
668
CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL,
sys/dev/ic/i82557.c
675
CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS);
sys/dev/ic/i82557.c
678
CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0);
sys/dev/ic/i82557.c
703
CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS);
sys/dev/ic/i82557.c
716
CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL,
sys/dev/ic/i82557.c
722
CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg);
sys/dev/ic/i82557.c
725
CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0);
sys/dev/ic/i82557.c
740
CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS);
sys/dev/ic/i82557.c
744
CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0);
sys/dev/ic/i82557.c
748
CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS);
sys/dev/ic/i82557.c
752
CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0);
sys/dev/ic/i82557.c
756
CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS);
sys/dev/ic/i82557.c
764
CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0);
sys/dev/ic/i82557.c
768
CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS);
sys/dev/ic/i82557.c
771
CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0);
sys/dev/ic/rtl8169.c
1603
CSR_WRITE_2(sc, RTK_ISR, status);
sys/dev/ic/rtl8169.c
1990
CSR_WRITE_2(sc, RTK_CPLUS_CMD, cfg);
sys/dev/ic/rtl8169.c
1995
CSR_WRITE_2(sc, RTK_IM, 0x0000);
sys/dev/ic/rtl8169.c
1997
CSR_WRITE_2(sc, RTK_IM, 0x5151);
sys/dev/ic/rtl8169.c
2102
CSR_WRITE_2(sc, RTK_IMR, 0);
sys/dev/ic/rtl8169.c
2104
CSR_WRITE_2(sc, RTK_IMR, RTK_INTRS_IM_HW);
sys/dev/ic/rtl8169.c
2106
CSR_WRITE_2(sc, RTK_IMR, RTK_INTRS_CPLUS);
sys/dev/ic/rtl8169.c
2171
CSR_WRITE_2(sc, RTK_MAXRXPKTLEN, 16383);
sys/dev/ic/rtl8169.c
2335
CSR_WRITE_2(sc, RTK_IMR, 0x0000);
sys/dev/ic/rtl8169.c
2336
CSR_WRITE_2(sc, RTK_ISR, 0xFFFF);
sys/dev/ic/rtl8169.c
407
CSR_WRITE_2(sc, re8139_reg, val);
sys/dev/ic/rtl8169.c
516
CSR_WRITE_2(sc, RTK_ISR, 0xFFFF);
sys/dev/ic/rtl81x9.c
1078
CSR_WRITE_2(sc, RTK_CURRXADDR, (new_rx - 16) % RTK_RXBUFLEN);
sys/dev/ic/rtl81x9.c
1178
CSR_WRITE_2(sc, RTK_IMR, 0x0000);
sys/dev/ic/rtl81x9.c
1189
CSR_WRITE_2(sc, RTK_ISR, status);
sys/dev/ic/rtl81x9.c
1214
CSR_WRITE_2(sc, RTK_IMR, RTK_INTRS);
sys/dev/ic/rtl81x9.c
1409
CSR_WRITE_2(sc, RTK_IMR, RTK_INTRS);
sys/dev/ic/rtl81x9.c
1491
CSR_WRITE_2(sc, RTK_IMR, 0x0000);
sys/dev/ic/rtl81x9.c
295
CSR_WRITE_2(sc, RTK_MII, 0);
sys/dev/ic/rtl81x9.c
497
CSR_WRITE_2(sc, rtk8139_reg, val);
sys/dev/ic/rtl81x9.c
970
CSR_WRITE_2(sc, RTK_COMMAND, RTK_CMD_TX_ENB);
sys/dev/ic/rtl81x9.c
971
CSR_WRITE_2(sc, RTK_COMMAND,
sys/dev/ic/wi.c
1001
CSR_WRITE_2(sc, WI_EVENT_ACK, WI_EV_CMD);
sys/dev/ic/wi.c
1031
CSR_WRITE_2(sc, WI_INT_EN, 0);
sys/dev/ic/wi.c
1310
CSR_WRITE_2(sc, WI_INT_EN, 0);
sys/dev/ic/wi.c
1311
CSR_WRITE_2(sc, WI_EVENT_ACK, ~0);
sys/dev/ic/wi.c
2807
CSR_WRITE_2(sc, WI_PARAM0, val0);
sys/dev/ic/wi.c
2808
CSR_WRITE_2(sc, WI_PARAM1, val1);
sys/dev/ic/wi.c
2809
CSR_WRITE_2(sc, WI_PARAM2, val2);
sys/dev/ic/wi.c
2810
CSR_WRITE_2(sc, WI_COMMAND, cmd);
sys/dev/ic/wi.c
2904
CSR_WRITE_2(sc, WI_EVENT_ACK, WI_EV_CMD);
sys/dev/ic/wi.c
2924
CSR_WRITE_2(sc, WI_SEL0, id);
sys/dev/ic/wi.c
2925
CSR_WRITE_2(sc, WI_OFF0, off);
sys/dev/ic/wi.c
3018
CSR_WRITE_2(sc, WI_DATA0, 0x1234);
sys/dev/ic/wi.c
3019
CSR_WRITE_2(sc, WI_DATA0, 0x5678);
sys/dev/ic/wi.c
3080
CSR_WRITE_2(sc, WI_EVENT_ACK, WI_EV_ALLOC);
sys/dev/ic/wi.c
388
CSR_WRITE_2(sc, WI_INT_EN, 0);
sys/dev/ic/wi.c
389
CSR_WRITE_2(sc, WI_EVENT_ACK, ~0);
sys/dev/ic/wi.c
645
CSR_WRITE_2(sc, WI_INT_EN, 0);
sys/dev/ic/wi.c
646
CSR_WRITE_2(sc, WI_EVENT_ACK, ~0);
sys/dev/ic/wi.c
653
CSR_WRITE_2(sc, WI_INT_EN, 0);
sys/dev/ic/wi.c
663
CSR_WRITE_2(sc, WI_INT_EN, WI_INTRS);
sys/dev/ic/wi.c
685
CSR_WRITE_2(sc, WI_EVENT_ACK, ~0);
sys/dev/ic/wi.c
718
CSR_WRITE_2(sc, WI_EVENT_ACK, sc->sc_status);
sys/dev/ic/wi.c
740
CSR_WRITE_2(sc, WI_INT_EN, WI_INTRS);
sys/dev/ic/wi.c
960
CSR_WRITE_2(sc, WI_INT_EN, WI_INTRS);
sys/dev/pci/if_age.c
1728
CSR_WRITE_2(sc, AGE_IM_TIMER, AGE_USECS(sc->age_int_mod));
sys/dev/pci/if_age.c
1739
CSR_WRITE_2(sc, AGE_INTR_CLR_TIMER, AGE_USECS(1000));
sys/dev/pci/if_alc.c
1042
CSR_WRITE_2(sc, ALC_GPHY_CFG, GPHY_CFG_EXT_RESET |
sys/dev/pci/if_alc.c
1085
CSR_WRITE_2(sc, sc->alc_expcap + PCIE_LCSR,
sys/dev/pci/if_alc.c
819
CSR_WRITE_2(sc, ALC_GPHY_CFG, GPHY_CFG_SEL_ANA_RESET);
sys/dev/pci/if_alc.c
823
CSR_WRITE_2(sc, ALC_GPHY_CFG, GPHY_CFG_EXT_RESET |
sys/dev/pci/if_ale.c
1702
CSR_WRITE_2(sc, ALE_INTR_CLR_TIMER, ALE_USECS(1000));
sys/dev/pci/if_ale.c
339
CSR_WRITE_2(sc, ALE_GPHY_CTRL,
sys/dev/pci/if_ale.c
343
CSR_WRITE_2(sc, ALE_GPHY_CTRL,
sys/dev/pci/if_ipwreg.h
345
CSR_WRITE_2((sc), IPW_CSR_INDIRECT_DATA, (val)); \
sys/dev/pci/if_iwireg.h
569
CSR_WRITE_2((sc), IWI_CSR_INDIRECT_DATA, (val)); \
sys/dev/pci/if_kse.c
1356
CSR_WRITE_2(sc, P1CR4, p1cr4);
sys/dev/pci/if_kse.c
1436
CSR_WRITE_2(sc, phy1csr[reg], val);
sys/dev/pci/if_kse.c
1509
CSR_WRITE_2(sc, IACR, reg);
sys/dev/pci/if_kse.c
1525
CSR_WRITE_2(sc, IACR, EVCNTBR + 0x100 + p);
sys/dev/pci/if_kse.c
1527
CSR_WRITE_2(sc, IACR, EVCNTBR + 0x100 + p * 3 + 1);
sys/dev/pci/if_kse.c
1543
CSR_WRITE_2(sc, IACR, reg);
sys/dev/pci/if_kse.c
1550
CSR_WRITE_2(sc, IACR, EVCNTBR + 0x100 + p);
sys/dev/pci/if_kse.c
1552
CSR_WRITE_2(sc, IACR, EVCNTBR + 0x100 + p * 3 + 1);
sys/dev/pci/if_kse.c
451
CSR_WRITE_2(sc, SIDER, 1);
sys/dev/pci/if_kse.c
802
CSR_WRITE_2(sc, SGCR3, i | CR3_USEFC);
sys/dev/pci/if_kse.c
878
CSR_WRITE_2(sc, GRR, 1);
sys/dev/pci/if_kse.c
880
CSR_WRITE_2(sc, GRR, 0);
sys/dev/pci/if_kse.c
883
CSR_WRITE_2(sc, SIDER, 1);
sys/dev/pci/if_msk.c
1003
CSR_WRITE_2(sc, SK_LINK_CTRL, SK_LINK_RESET_SET);
sys/dev/pci/if_msk.c
1004
CSR_WRITE_2(sc, SK_LINK_CTRL + SK_WIN_LEN, SK_LINK_RESET_SET);
sys/dev/pci/if_msk.c
1006
CSR_WRITE_2(sc, SK_LINK_CTRL, SK_LINK_RESET_CLEAR);
sys/dev/pci/if_msk.c
1007
CSR_WRITE_2(sc, SK_LINK_CTRL + SK_WIN_LEN, SK_LINK_RESET_CLEAR);
sys/dev/pci/if_msk.c
1010
CSR_WRITE_2(sc, SK_GMAC_CTRL, SK_GMAC_BYP_MACSECRX |
sys/dev/pci/if_msk.c
1790
CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_ON);
sys/dev/pci/if_msk.c
2085
CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_OFF);
sys/dev/pci/if_msk.c
2098
CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_ON);
sys/dev/pci/if_msk.c
271
CSR_WRITE_2(sc, reg, x);
sys/dev/pci/if_msk.c
942
CSR_WRITE_2(sc, SK_Y2_ASF_HCU_CCSR, status);
sys/dev/pci/if_msk.c
946
CSR_WRITE_2(sc, SK_CSR, SK_CSR_ASF_OFF);
sys/dev/pci/if_msk.c
961
CSR_WRITE_2(sc, SK_CSR, SK_CSR_WOL_ON);
sys/dev/pci/if_sk.c
1153
CSR_WRITE_2(sc, SK_CSR, SK_CSR_SW_RESET);
sys/dev/pci/if_sk.c
1154
CSR_WRITE_2(sc, SK_CSR, SK_CSR_MASTER_RESET);
sys/dev/pci/if_sk.c
1156
CSR_WRITE_2(sc, SK_LINK_CTRL, SK_LINK_RESET_SET);
sys/dev/pci/if_sk.c
1159
CSR_WRITE_2(sc, SK_CSR, SK_CSR_SW_UNRESET);
sys/dev/pci/if_sk.c
1161
CSR_WRITE_2(sc, SK_CSR, SK_CSR_MASTER_UNRESET);
sys/dev/pci/if_sk.c
1163
CSR_WRITE_2(sc, SK_LINK_CTRL, SK_LINK_RESET_CLEAR);
sys/dev/pci/if_sk.c
1795
CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_ON);
sys/dev/pci/if_sk.c
2018
CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_OFF);
sys/dev/pci/if_sk.c
2974
CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_OFF);
sys/dev/pci/if_sk.c
2987
CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_ON);
sys/dev/pci/if_sk.c
307
CSR_WRITE_2(sc, SK_WIN_BASE + SK_REG(reg), x);
sys/dev/pci/if_sk.c
309
CSR_WRITE_2(sc, reg, x);
sys/dev/pci/if_stge.c
1161
CSR_WRITE_2(sc, STGE_IntEnable, sc->sc_IntEnable);
sys/dev/pci/if_stge.c
1597
CSR_WRITE_2(sc, STGE_TxStartThresh, sc->sc_txthresh);
sys/dev/pci/if_stge.c
1604
CSR_WRITE_2(sc, STGE_RxEarlyThresh, 0x7ff);
sys/dev/pci/if_stge.c
1625
CSR_WRITE_2(sc, STGE_IntStatus, 0xffff);
sys/dev/pci/if_stge.c
1626
CSR_WRITE_2(sc, STGE_IntEnable, sc->sc_IntEnable);
sys/dev/pci/if_stge.c
1640
CSR_WRITE_2(sc, STGE_FlowOnTresh, 29696 / 16);
sys/dev/pci/if_stge.c
1641
CSR_WRITE_2(sc, STGE_FlowOffThresh, 3056 / 16);
sys/dev/pci/if_stge.c
1646
CSR_WRITE_2(sc, STGE_MaxFrameSize,
sys/dev/pci/if_stge.c
1667
CSR_WRITE_2(sc, STGE_DebugCtrl,
sys/dev/pci/if_stge.c
1671
CSR_WRITE_2(sc, STGE_DebugCtrl,
sys/dev/pci/if_stge.c
1674
CSR_WRITE_2(sc, STGE_DebugCtrl,
sys/dev/pci/if_stge.c
1745
CSR_WRITE_2(sc, STGE_IntEnable, 0);
sys/dev/pci/if_stge.c
1810
CSR_WRITE_2(sc, STGE_EepromCtrl,
sys/dev/pci/if_stge.c
1954
CSR_WRITE_2(sc, STGE_ReceiveMode, sc->sc_ReceiveMode);
sys/dev/pci/if_vge.c
1358
CSR_WRITE_2(sc, VGE_RXDESC_RESIDUECNT, lim);
sys/dev/pci/if_vge.c
1715
CSR_WRITE_2(sc, VGE_TXQCSRS, VGE_TXQCSR_WAK0);
sys/dev/pci/if_vge.c
1806
CSR_WRITE_2(sc, VGE_TXDESCNUM, VGE_NTXDESC - 1);
sys/dev/pci/if_vge.c
1809
CSR_WRITE_2(sc, VGE_RXDESCNUM, VGE_NRXDESC - 1);
sys/dev/pci/if_vge.c
1810
CSR_WRITE_2(sc, VGE_RXDESC_RESIDUECNT, VGE_NRXDESC);
sys/dev/pci/if_vge.c
1817
CSR_WRITE_2(sc, VGE_TXQCSRS, VGE_TXQCSR_RUN0);
sys/dev/pci/if_vge.c
1860
CSR_WRITE_2(sc, VGE_SSTIMER, 400);
sys/dev/pci/if_vge.c
2065
CSR_WRITE_2(sc, VGE_TXQCSRC, 0xFFFF);
sys/dev/pci/if_vge.c
277
CSR_WRITE_2((sc), (reg), CSR_READ_2((sc), (reg)) | (x))
sys/dev/pci/if_vge.c
284
CSR_WRITE_2((sc), (reg), CSR_READ_2((sc), (reg)) & ~(x))
sys/dev/pci/if_vge.c
521
CSR_WRITE_2(sc, VGE_MIIDATA, val);
sys/dev/pci/if_vr.c
1266
CSR_WRITE_2(sc, VR_COMMAND, VR_CMD_TX_NOPOLL | VR_CMD_START |
sys/dev/pci/if_vr.c
1271
CSR_WRITE_2(sc, VR_ISR, 0xFFFF);
sys/dev/pci/if_vr.c
1272
CSR_WRITE_2(sc, VR_IMR, VR_INTRS);
sys/dev/pci/if_vr.c
1402
CSR_WRITE_2(sc, VR_IMR, 0x0000);
sys/dev/pci/if_vr.c
337
CSR_WRITE_2(sc, reg, \
sys/dev/pci/if_vr.c
341
CSR_WRITE_2(sc, reg, \
sys/dev/pci/if_vr.c
926
CSR_WRITE_2(sc, VR_IMR, 0x0000);
sys/dev/pci/if_vr.c
931
CSR_WRITE_2(sc, VR_ISR, status);
sys/dev/pci/if_vr.c
989
CSR_WRITE_2(sc, VR_IMR, VR_INTRS);
sys/dev/pci/if_vte.c
1181
CSR_WRITE_2(sc, VTE_MRDCR, prog |
sys/dev/pci/if_vte.c
1213
CSR_WRITE_2(sc, VTE_MCR1, mcr | MCR1_MAC_RESET);
sys/dev/pci/if_vte.c
1226
CSR_WRITE_2(sc, VTE_MACSM, 0x0002);
sys/dev/pci/if_vte.c
1227
CSR_WRITE_2(sc, VTE_MACSM, 0);
sys/dev/pci/if_vte.c
1236
CSR_WRITE_2(sc, VTE_MDCSC, mdcsc);
sys/dev/pci/if_vte.c
1285
CSR_WRITE_2(sc, VTE_MID0L, eaddr[1] << 8 | eaddr[0]);
sys/dev/pci/if_vte.c
1286
CSR_WRITE_2(sc, VTE_MID0M, eaddr[3] << 8 | eaddr[2]);
sys/dev/pci/if_vte.c
1287
CSR_WRITE_2(sc, VTE_MID0H, eaddr[5] << 8 | eaddr[4]);
sys/dev/pci/if_vte.c
1292
CSR_WRITE_2(sc, VTE_MTDSA1, paddr >> 16);
sys/dev/pci/if_vte.c
1293
CSR_WRITE_2(sc, VTE_MTDSA0, paddr & 0xFFFF);
sys/dev/pci/if_vte.c
1298
CSR_WRITE_2(sc, VTE_MRDSA1, paddr >> 16);
sys/dev/pci/if_vte.c
1299
CSR_WRITE_2(sc, VTE_MRDSA0, paddr & 0xFFFF);
sys/dev/pci/if_vte.c
1306
CSR_WRITE_2(sc, VTE_MRDCR, (VTE_RX_RING_CNT & VTE_MRDCR_RESIDUE_MASK) |
sys/dev/pci/if_vte.c
1319
CSR_WRITE_2(sc, VTE_MRBSR, VTE_RX_BUF_SIZE_MAX);
sys/dev/pci/if_vte.c
1322
CSR_WRITE_2(sc, VTE_MBCR, MBCR_FIFO_XFER_LENGTH_16 |
sys/dev/pci/if_vte.c
1333
CSR_WRITE_2(sc, VTE_MCR0, MCR0_ACCPT_LONG_PKT);
sys/dev/pci/if_vte.c
1340
CSR_WRITE_2(sc, VTE_MCR1, MCR1_PKT_LENGTH_1537 |
sys/dev/pci/if_vte.c
1347
CSR_WRITE_2(sc, VTE_MRICR, 0);
sys/dev/pci/if_vte.c
1348
CSR_WRITE_2(sc, VTE_MTICR, 0);
sys/dev/pci/if_vte.c
1351
CSR_WRITE_2(sc, VTE_MECIER, VTE_MECIER_INTRS);
sys/dev/pci/if_vte.c
1356
CSR_WRITE_2(sc, VTE_MIER, VTE_INTRS);
sys/dev/pci/if_vte.c
1357
CSR_WRITE_2(sc, VTE_MISR, 0);
sys/dev/pci/if_vte.c
1401
CSR_WRITE_2(sc, VTE_MIER, 0);
sys/dev/pci/if_vte.c
1402
CSR_WRITE_2(sc, VTE_MECIER, 0);
sys/dev/pci/if_vte.c
1456
CSR_WRITE_2(sc, VTE_MCR0, mcr);
sys/dev/pci/if_vte.c
1481
CSR_WRITE_2(sc, VTE_MCR0, mcr);
sys/dev/pci/if_vte.c
1655
CSR_WRITE_2(sc, VTE_MAR0, mchash[0]);
sys/dev/pci/if_vte.c
1656
CSR_WRITE_2(sc, VTE_MAR1, mchash[1]);
sys/dev/pci/if_vte.c
1657
CSR_WRITE_2(sc, VTE_MAR2, mchash[2]);
sys/dev/pci/if_vte.c
1658
CSR_WRITE_2(sc, VTE_MAR3, mchash[3]);
sys/dev/pci/if_vte.c
1662
CSR_WRITE_2(sc, VTE_RXFILTER_PEEFECT_BASE + 8 * i + 0,
sys/dev/pci/if_vte.c
1664
CSR_WRITE_2(sc, VTE_RXFILTER_PEEFECT_BASE + 8 * i + 2,
sys/dev/pci/if_vte.c
1666
CSR_WRITE_2(sc, VTE_RXFILTER_PEEFECT_BASE + 8 * i + 4,
sys/dev/pci/if_vte.c
1670
CSR_WRITE_2(sc, VTE_MCR0, mcr);
sys/dev/pci/if_vte.c
343
CSR_WRITE_2(sc, VTE_MMDIO, MMDIO_READ |
sys/dev/pci/if_vte.c
366
CSR_WRITE_2(sc, VTE_MMWD, val);
sys/dev/pci/if_vte.c
367
CSR_WRITE_2(sc, VTE_MMDIO, MMDIO_WRITE |
sys/dev/pci/if_vte.c
419
CSR_WRITE_2(sc, VTE_MRICR, val);
sys/dev/pci/if_vte.c
427
CSR_WRITE_2(sc, VTE_MTICR, val);
sys/dev/pci/if_vte.c
814
CSR_WRITE_2(sc, VTE_TX_POLL, TX_POLL_START);
sys/dev/pci/if_vte.c
890
CSR_WRITE_2(sc, VTE_MCR0, mcr);
sys/dev/pci/if_vte.c
976
CSR_WRITE_2(sc, VTE_MIER, 0);
sys/dev/pci/if_vte.c
996
CSR_WRITE_2(sc, VTE_MIER, VTE_INTRS);
sys/dev/pci/if_wi_pci.c
302
CSR_WRITE_2(sc, WI_INT_EN, 0);
sys/dev/pci/if_wi_pci.c
303
CSR_WRITE_2(sc, WI_EVENT_ACK, 0xFFFF);
sys/dev/pcmcia/if_wi_pcmcia.c
449
CSR_WRITE_2(sc, WI_PARAM0, WI_AUX_KEY0);
sys/dev/pcmcia/if_wi_pcmcia.c
450
CSR_WRITE_2(sc, WI_PARAM1, WI_AUX_KEY1);
sys/dev/pcmcia/if_wi_pcmcia.c
451
CSR_WRITE_2(sc, WI_PARAM2, WI_AUX_KEY2);
sys/dev/pcmcia/if_wi_pcmcia.c
452
CSR_WRITE_2(sc, WI_CNTL, WI_CNTL_AUX_ENA_CNTL);
sys/dev/pcmcia/if_wi_pcmcia.c
456
CSR_WRITE_2(sc, WI_PARAM0, 0);
sys/dev/pcmcia/if_wi_pcmcia.c
457
CSR_WRITE_2(sc, WI_PARAM1, 0);
sys/dev/pcmcia/if_wi_pcmcia.c
458
CSR_WRITE_2(sc, WI_PARAM2, 0);
sys/dev/pcmcia/if_wi_pcmcia.c
459
CSR_WRITE_2(sc, WI_COMMAND, WI_CMD_READEE);
sys/dev/pcmcia/if_wi_pcmcia.c
465
CSR_WRITE_2(sc, WI_EVENT_ACK, WI_EV_CMD);
sys/dev/pcmcia/if_wi_pcmcia.c
467
CSR_WRITE_2(sc, WI_AUX_PAGE, WI_SBCF_PDIADDR / WI_AUX_PGSZ);
sys/dev/pcmcia/if_wi_pcmcia.c
468
CSR_WRITE_2(sc, WI_AUX_OFFSET, WI_SBCF_PDIADDR % WI_AUX_PGSZ);
sys/dev/pcmcia/if_wi_pcmcia.c
507
CSR_WRITE_2(sc, WI_AUX_PAGE, addr / WI_AUX_PGSZ);
sys/dev/pcmcia/if_wi_pcmcia.c
508
CSR_WRITE_2(sc, WI_AUX_OFFSET, addr % WI_AUX_PGSZ);
sys/dev/pcmcia/if_wi_pcmcia.c
530
CSR_WRITE_2(sc, WI_AUX_PAGE, addr / WI_AUX_PGSZ);
sys/dev/pcmcia/if_wi_pcmcia.c
531
CSR_WRITE_2(sc, WI_AUX_OFFSET, addr % WI_AUX_PGSZ);
sys/dev/pcmcia/if_wi_pcmcia.c
545
CSR_WRITE_2(sc, WI_COR, WI_COR_RESET);
sys/dev/pcmcia/if_wi_pcmcia.c
549
CSR_WRITE_2(sc, WI_HCR, hcr);
sys/dev/pcmcia/if_wi_pcmcia.c
551
CSR_WRITE_2(sc, WI_COR, WI_COR_IOMODE);