CSR_READ_1
msr = CSR_READ_1(regsp, IMXUART_REG_MSR);
(void)CSR_READ_1(&sc->sc_regs, IMXUART_REG_IIR);
(void)CSR_READ_1(&sc->sc_regs, ZYNQUART_REG_IIR);
*cmd->c_buf++ = CSR_READ_1(sc, MMC_RXFIFO);
val = CSR_READ_1(l, PID0);
val |= CSR_READ_1(l, PID1) << 8;
val |= CSR_READ_1(l, VID0) << 16;
val |= CSR_READ_1(l, VID1) << 24;
val = CSR_READ_1(l, CHIPR);
val = CSR_READ_1(l, ISR);
} while (NCR_RST & CSR_READ_1(l, NCR));
} while (NCR_RST & CSR_READ_1(l, NCR));
(void) CSR_READ_1(l, NSR);
val = CSR_READ_1(l, NSR);
val = CSR_READ_1(l, FCR);
val = CSR_READ_1(l, TCR);
val = CSR_READ_1(l, ISR);
stat = CSR_READ_1(l, RSR);
v = CSR_READ_1(l, EPCR);
v = (CSR_READ_1(l, EPDRH) << 8) | CSR_READ_1(l, EPDRL);
v = CSR_READ_1(l, EPCR);
(void)CSR_READ_1(chan->alt);
(void)CSR_READ_1(chan->alt);
(void)CSR_READ_1(chan->alt);
(void)CSR_READ_1(chan->alt);
sts = CSR_READ_1(chan->cmd + _STS);
sts = CSR_READ_1(chan->cmd + _STS);
(void)CSR_READ_1(chan->alt);
(void)CSR_READ_1(chan->alt);
(void)CSR_READ_1(chan->alt);
return CSR_READ_1(chan->cmd + _NSECT);
(void)CSR_READ_1(chan->alt);
(void)CSR_READ_1(chan->cmd + _STS);
(void)CSR_READ_1(chan->cmd + _STS);
ruscus = CSR_READ_1(l, FXP_CSR_SCB_RUSCUS);
while (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) && --loop > 0)
val = CSR_READ_1(l, VR_CTL1);
l->phy = CSR_READ_1(l, VR_MIICFG) & 0x1f;
en[0] = CSR_READ_1(l, VR_PAR0);
en[1] = CSR_READ_1(l, VR_PAR1);
en[2] = CSR_READ_1(l, VR_PAR2);
en[3] = CSR_READ_1(l, VR_PAR3);
en[4] = CSR_READ_1(l, VR_PAR4);
en[5] = CSR_READ_1(l, VR_PAR5);
v = CSR_READ_1(l, VR_MIISR);
v = CSR_READ_1(l, VR_MIISR);
v = CSR_READ_1(l, VR_MIISR);
v = CSR_READ_1(l, VR_MIICR);
v = CSR_READ_1(l, VR_MIICR);
val = CSR_READ_1(l, RGE_CR);
en[0] = CSR_READ_1(l, RGE_IDR0);
en[1] = CSR_READ_1(l, RGE_IDR1);
en[2] = CSR_READ_1(l, RGE_IDR2);
en[3] = CSR_READ_1(l, RGE_IDR3);
en[4] = CSR_READ_1(l, RGE_IDR4);
en[5] = CSR_READ_1(l, RGE_IDR5);
val = CSR_READ_1(l, RGE_PHYSR);
en[i] = CSR_READ_1(l, SK_MAC0 + i);
en[i] = CSR_READ_1(l, STGE_StationAddress0 + i);
reg = CSR_READ_1(l, STGE_PhyCtrl);
data |= !!(CSR_READ_1(l, STGE_PhyCtrl) & PC_MgmtData);
l->phyctrl_saved = CSR_READ_1(l, STGE_PhyCtrl) &
val = CSR_READ_1(l, VR_CTL1);
l->phy = CSR_READ_1(l, VR_MIICFG) & 0x1f;
en[0] = CSR_READ_1(l, VR_PAR0);
en[1] = CSR_READ_1(l, VR_PAR1);
en[2] = CSR_READ_1(l, VR_PAR2);
en[3] = CSR_READ_1(l, VR_PAR3);
en[4] = CSR_READ_1(l, VR_PAR4);
en[5] = CSR_READ_1(l, VR_PAR5);
while (--loop > 0 && (i = CSR_READ_1(l, VR_CAMCTL)) & CAMCTL_WR)
v = CSR_READ_1(l, VR_MIISR);
v = CSR_READ_1(l, VR_MIISR);
v = CSR_READ_1(l, VR_MIISR);
v = CSR_READ_1(l, VR_MIICR);
v = CSR_READ_1(l, VR_MIICR);
sc->sc_msr = CSR_READ_1(&sc->sc_regs, COM_REG_MSR);
while (ISSET(CSR_READ_1(regsp, COM_REG_LSR), LSR_RXRDY)
CSR_READ_1(regsp, COM_REG_RXDATA);
fifo = CSR_READ_1(regsp, COM_REG_FIFO) & (FIFO_TRIGGER_1 |
iir = CSR_READ_1(regsp, COM_REG_IIR);
(CSR_READ_1(regsp, COM_REG_USR) & 0x1) != 0; timeout--) {
iir = CSR_READ_1(regsp, COM_REG_IIR);
(void)CSR_READ_1(regsp, COM_REG_USR);
} else if ((CSR_READ_1(regsp, COM_REG_USR) & 0x1) != 0) {
(CSR_READ_1(regsp, COM_REG_HALT) & HALT_CHCFG_UD) != 0;
CSR_READ_1(regsp, COM_REG_HALT),
CSR_READ_1(regsp, COM_REG_USR));
(void)CSR_READ_1(regsp, COM_REG_USR);
lsr = CSR_READ_1(regsp, COM_REG_LSR);
put[0] = CSR_READ_1(regsp, COM_REG_RXDATA);
lsr = CSR_READ_1(regsp, COM_REG_LSR);
(void) CSR_READ_1(regsp, COM_REG_RXDATA);
msr = CSR_READ_1(regsp, COM_REG_MSR);
CSR_READ_1(regsp, COM_REG_IIR)), IIR_NOPEND) &&
lsr = CSR_READ_1(regsp, COM_REG_LSR);
if (!ISSET((iir = CSR_READ_1(regsp, COM_REG_IIR)), IIR_NOPEND))
if (!ISSET(stat = CSR_READ_1(regsp, COM_REG_LSR), LSR_RXRDY)) {
c = CSR_READ_1(regsp, COM_REG_RXDATA);
stat = CSR_READ_1(regsp, COM_REG_IIR);
&& ISSET(stat = CSR_READ_1(regsp, COM_REG_LSR), LSR_RXRDY)) {
cin = CSR_READ_1(regsp, COM_REG_RXDATA);
stat = CSR_READ_1(regsp, COM_REG_IIR);
while (!ISSET(CSR_READ_1(regsp, COM_REG_LSR), LSR_TXRDY) && --timo)
(void)CSR_READ_1(&sc->sc_regs, COM_REG_IIR);
if ((CSR_READ_1(regs, COM_REG_LCR) != LCR_8BITS) ||
(CSR_READ_1(regs, COM_REG_IIR) & 0x38))
if (ISSET(CSR_READ_1(regsp, COM_REG_IIR), IIR_FIFO_MASK)
if (ISSET(CSR_READ_1(regsp, COM_REG_FIFO), FIFO_TRIGGER_14)
lcr = CSR_READ_1(regsp, COM_REG_LCR);
if (CSR_READ_1(regsp, COM_REG_EFR) == 0) {
if (CSR_READ_1(regsp, COM_REG_EFR) == 0) {
lcr = CSR_READ_1(regsp, COM_REG_LCR);
iir1 = CSR_READ_1(regsp, COM_REG_IIR);
iir2 = CSR_READ_1(regsp, COM_REG_IIR);
(void) CSR_READ_1(regsp, COM_REG_IIR);
statack = CSR_READ_1(sc, FXP_CSR_SCB_STATACK);
while ((statack = CSR_READ_1(sc, FXP_CSR_SCB_STATACK)) != 0) {
if (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) == 0) {
while ((CSR_READ_1(sc, FXP_CSR_SCB_RUSCUS) >> 6) ==
while (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) && --i)
switch (CSR_READ_1(sc, RTK_CFG2_BUSFREQ) & 0x7) {
*val = CSR_READ_1(sc, RTK_GMEDIASTAT);
*val = CSR_READ_1(sc, RTK_MEDIASTAT);
if ((CSR_READ_1(sc, RTK_COMMAND) & RTK_CMD_RESET) == 0)
eaddr[i] = CSR_READ_1(sc, RTK_IDR0 + i);
eaddr[i] = CSR_READ_1(sc, RTK_IDR0 + i);
CSR_WRITE_1(sc, RTK_PMCH, CSR_READ_1(sc, RTK_PMCH) | 0x80);
CSR_READ_1(sc, RTK_EECMD) | (x))
CSR_READ_1(sc, RTK_EECMD) & ~(x))
if (CSR_READ_1(sc, RTK_EECMD) & RTK_EE_DATAOUT)
CSR_READ_1(sc, RTK_MII) | (x))
CSR_READ_1(sc, RTK_MII) & ~(x))
if ((CSR_READ_1(sc, RTK_COMMAND) & RTK_CMD_RESET) == 0)
while ((CSR_READ_1(sc, RTK_COMMAND) & RTK_CMD_EMPTY_RXBUF) == 0) {
return CSR_READ_1(sc, IPW_CSR_INDIRECT_DATA);
*datap = CSR_READ_1(sc, IPW_CSR_INDIRECT_DATA + (offset & 3));
return CSR_READ_1(sc, IWI_CSR_INDIRECT_DATA);
DPRINTFN(2, ("mskc_reset: sk_csr=%x\n", CSR_READ_1(sc, SK_CSR)));
return CSR_READ_1(sc, reg);
return CSR_READ_1(sc, SK_WIN_BASE + SK_REG(reg));
return CSR_READ_1(sc, reg);
return (CSR_READ_1(sc, STGE_PhyCtrl));
sc->sc_PhyCtrl = CSR_READ_1(sc, STGE_PhyCtrl) &
dctl = CSR_READ_1(sc, VGE_DIAGCTL);
val = CSR_READ_1(sc, VGE_PWRSTAT);
val = CSR_READ_1(sc, VGE_PWRSTAT);
CSR_WRITE_1((sc), (reg), CSR_READ_1((sc), (reg)) | (x))
CSR_WRITE_1((sc), (reg), CSR_READ_1((sc), (reg)) & ~(x))
if (CSR_READ_1(sc, VGE_EECMD) & VGE_EECMD_EDONE)
if (CSR_READ_1(sc, VGE_MIISTS) & VGE_MIISTS_IIDL)
if (CSR_READ_1(sc, VGE_MIISTS) & VGE_MIISTS_IIDL)
if ((CSR_READ_1(sc, VGE_MIISTS) & VGE_MIISTS_IIDL) == 0)
if (phy != (CSR_READ_1(sc, VGE_MIICFG) & 0x1F))
if ((CSR_READ_1(sc, VGE_MIICMD) & VGE_MIICMD_RCMD) == 0)
if (phy != (CSR_READ_1(sc, VGE_MIICFG) & 0x1F))
if ((CSR_READ_1(sc, VGE_MIICMD) & VGE_MIICMD_WCMD) == 0)
if ((CSR_READ_1(sc, VGE_CAMCTL) & VGE_CAMCTL_WRITE) == 0)
if ((CSR_READ_1(sc, VGE_CRS1) & VGE_CR1_SOFTRESET) == 0)
if ((CSR_READ_1(sc, VGE_EECSR) & VGE_EECSR_RELOAD) == 0)
mac |= (eaddr[i] = CSR_READ_1(sc, VR_PAR0 + i));
eaddr[i] = CSR_READ_1(sc, VR_PAR0 + i);
CSR_READ_1(sc, reg) | (x))
CSR_READ_1(sc, reg) & ~(x))
return (CSR_READ_1(sc, VR_MIICMD));
rxfilt = CSR_READ_1(sc, VR_RXCFG);
status = CSR_READ_1(sc, SBT_REG_ISTAT);