sys/arch/sgimips/dev/scn.c

461

sc->sc_chbase[CH_CR] = CR_CMD_MR1;

sys/arch/sgimips/dev/scn.c

469

sc->sc_chbase[CH_CR] = CR_CMD_MR1;

sys/arch/sgimips/dev/scn.c

850

ch_base[CH_CR] = CR_CMD_MR1;

sys/arch/sgimips/dev/scn.c

854

ch_base[CH_CR] = CR_CMD_MR1;

sys/arch/sgimips/dev/scn.c

858

ch_base[CH_CR] = CR_CMD_MR1;

sys/arch/sgimips/dev/scn.c

866

ch_base[CH_CR] = CR_CMD_MR1;

sys/arch/sgimips/dev/scn.c

899

ch_base[CH_CR] = CR_CMD_MR1;

sys/arch/sgimips/dev/scn.c

975

ch_base[CH_CR] = CR_CMD_MR1;

sys/arch/vax/uba/qvaux.c

311

qvaux_write2(sc, sc->sc_qr.qr_ch_regs[0].qr_cr, CR_CMD_MR1 | CR_ENA_RX);

sys/arch/vax/uba/qvaux.c

323

qvaux_write2(sc, sc->sc_qr.qr_ch_regs[1].qr_cr, CR_CMD_MR1 | CR_ENA_RX);

sys/arch/vax/uba/qvaux.c

786

CR_CMD_MR1 | CR_ENA_RX); // reset to mr1