njsc32_write_2
njsc32_write_2(sc, NJSC32_REG_TRANSFER,
njsc32_write_2(sc, NJSC32_REG_TRANSFER, cmd->c_xferctl);
njsc32_write_2(sc, NJSC32_REG_COMMAND_CONTROL,
njsc32_write_2(sc, NJSC32_REG_TIMER, NJSC32_ARBITRATION_RETRY_TIME);
out: njsc32_write_2(sc, NJSC32_REG_TRANSFER, 0);
njsc32_write_2(sc, NJSC32_REG_IRQ, 0);
njsc32_write_2(sc, NJSC32_REG_IRQ, NJSC32_IRQ_MASK_ALL);
njsc32_write_2(sc, NJSC32_REG_TRANSFER,
njsc32_write_2(sc, NJSC32_REG_TRANSFER, cmd->c_xferctl);
njsc32_write_2(sc, NJSC32_REG_COMMAND_CONTROL, cctl);
njsc32_write_2(sc, NJSC32_REG_COMMAND_CONTROL, cctl);
njsc32_write_2(sc, NJSC32_REG_COMMAND_CONTROL, cctl);
njsc32_write_2(sc, NJSC32_REG_COMMAND_CONTROL, 0);
njsc32_write_2(sc, NJSC32_REG_COMMAND_CONTROL, cctl);
njsc32_write_2(sc, NJSC32_REG_IRQ, NJSC32_IRQ_MASK_ALL);
njsc32_write_2(sc, NJSC32_REG_TIMER, NJSC32_TIMER_STOP);
njsc32_write_2(sc, NJSC32_REG_EXECUTE_PHASE, 0);
njsc32_write_2(sc,
njsc32_write_2(sc, NJSC32_REG_IRQ, 0);
njsc32_write_2(sc, NJSC32_REG_IRQ, NJSC32_IRQ_MASK_ALL);
njsc32_write_2(sc, NJSC32_REG_TRANSFER, 0);
njsc32_write_2(sc, NJSC32_REG_TIMER, NJSC32_TIMER_STOP);
njsc32_write_2(sc, NJSC32_REG_TIMER, NJSC32_TIMER_STOP);
njsc32_write_2(sc, NJSC32_REG_SEL_TIMEOUT,
njsc32_write_2(sc, NJSC32_REG_TRANSFER, NJSC32_XFR_DUALEDGE_ENABLE);
njsc32_write_2(sc, NJSC32_REG_TRANSFER, 0); /* restore */
njsc32_write_2(sc, NJSC32_REG_COMMAND_CONTROL, NJSC32_CMD_CLEAR_CDB_FIFO_PTR);
njsc32_write_2(sc, NJSC32_REG_COMMAND_CONTROL,