njsc32_ireg_write_1
njsc32_ireg_write_1(sc, NJSC32_IREG_FIFO_THRESHOLD_FULL,
njsc32_ireg_write_1(sc, NJSC32_IREG_FIFO_THRESHOLD_EMPTY,
njsc32_ireg_write_1(sc, NJSC32_IREG_CLOCK, sc->sc_clk);
njsc32_ireg_write_1(sc, NJSC32_IREG_BM,
njsc32_ireg_write_1(sc, NJSC32_IREG_TERM_PWR, 0);
njsc32_ireg_write_1(sc, NJSC32_IREG_TERM_PWR,
njsc32_ireg_write_1(sc, NJSC32_IREG_EXT_PORT_DDR,
njsc32_ireg_write_1(sc, NJSC32_IREG_EXT_PORT,
njsc32_ireg_write_1(sc, NJSC32_IREG_EXT_PORT, NJSC32_EXTPORT_LED_ON);
njsc32_ireg_write_1(sc, NJSC32_IREG_EXT_PORT, NJSC32_EXTPORT_LED_OFF);