CPU_ISSUN4C
} else if (CPU_ISSUN4C) {
if (CPU_ISSUN4C) {
if (!CPU_ISSUN4C)
sc->sc_intr2ipl = CPU_ISSUN4C
sc->sc_intr2ipl = CPU_ISSUN4C ? intr_sbus2ipl_4c : intr_sbus2ipl_4m;
sc->sc_intr2ipl = CPU_ISSUN4C ? intr_sbus2ipl_4c : intr_sbus2ipl_4m;
#define ZS_DELAY() (CPU_ISSUN4C ? (0) : delay(2))
if (CPU_ISSUN4C || CPU_ISSUN4M) {
#define CPU_HAS_SUNMMU (CPU_ISSUN4 || CPU_ISSUN4C)
if (CPU_ISSUN4 || CPU_ISSUN4C)
} else if (CPU_ISSUN4C) {
if (CPU_ISSUN4C && device_is_a(dev, "sd"))
if (CPU_ISSUN4 || CPU_ISSUN4C) {
if (CPU_ISSUN4C) {
if (CPU_ISSUN4 || CPU_ISSUN4C) {
if (CPU_ISSUN4C) {
if (CPU_ISSUN4 || CPU_ISSUN4C) {
if (CPU_ISSUN4 || CPU_ISSUN4C)
if (CPU_ISSUN4C || CPU_ISSUN4) {
if (CPU_ISSUN4 || CPU_ISSUN4C) {
if (CPU_ISSUN4 || CPU_ISSUN4C) {
if (CPU_ISSUN4C) {
#define getsegmap(va) (CPU_ISSUN4C \
#define setsegmap(va, pmeg) (CPU_ISSUN4C \
if (CPU_ISSUN4C || CPU_ISSUN4) {
if (CPU_ISSUN4 || CPU_ISSUN4C) {
if (CPU_ISSUN4 || CPU_ISSUN4C) {
#define setsegmap(va, pmeg) (CPU_ISSUN4C \
} else if (CPU_ISSUN4C) {
if (CPU_ISSUN4C) {
if (!CPU_ISSUN4C)