mue_csr_write
mue_csr_write(un, hireg, 0);
mue_csr_write(un, loreg, pfiltbl[i][1]);
mue_csr_write(un, hireg, pfiltbl[i][0]);
mue_csr_write(un, reg, rxfilt);
mue_csr_write(un, reg, val);
mue_csr_write(un, MUE_MAC_RX, val);
mue_csr_write(un, reg, mue_csr_read(un, reg) | (x))
mue_csr_write(un, reg, mue_csr_read(un, reg) & ~(x))
mue_csr_write(un, MUE_MII_ACCESS, MUE_MII_ACCESS_READ |
mue_csr_write(un, MUE_MII_DATA, val);
mue_csr_write(un, MUE_MII_ACCESS, MUE_MII_ACCESS_WRITE |
mue_csr_write(un, (un->un_flags & LAN7500) ?
mue_csr_write(un, MUE_FLOW, flow);
mue_csr_write(un, MUE_E2P_CMD, MUE_E2P_CMD_READ | MUE_E2P_CMD_BUSY |
mue_csr_write(un, MUE_HW_CFG,
mue_csr_write(un, MUE_HW_CFG, val);
mue_csr_write(un, MUE_OTP_PWR_DN, 0);
mue_csr_write(un, MUE_OTP_ADDR1,
mue_csr_write(un, MUE_OTP_ADDR2,
mue_csr_write(un, MUE_OTP_FUNC_CMD, MUE_OTP_FUNC_CMD_READ);
mue_csr_write(un, MUE_OTP_CMD_GO, MUE_OTP_CMD_GO_GO);
mue_csr_write(un, MUE_DP_SEL,
mue_csr_write(un, MUE_DP_ADDR, addr + i);
mue_csr_write(un, MUE_DP_DATA, data[i]);
mue_csr_write(un, MUE_DP_CMD, MUE_DP_CMD_WRITE);
mue_csr_write(un, MUE_LTM_INDEX(i), idx[i]);
mue_csr_write(un, MUE_7500_BURST_CAP, val);
mue_csr_write(un, MUE_7500_BULKIN_DELAY,
mue_csr_write(un, MUE_7500_FCT_RX_FIFO_END, val);
mue_csr_write(un, MUE_7500_FCT_TX_FIFO_END, val);
mue_csr_write(un, MUE_7800_BURST_CAP, val);
mue_csr_write(un, MUE_7800_BULKIN_DELAY,
mue_csr_write(un, MUE_7800_FCT_RX_FIFO_END, val);
mue_csr_write(un, MUE_7800_FCT_TX_FIFO_END, val);
mue_csr_write(un, MUE_INT_STATUS, ~0);
mue_csr_write(un, (un->un_flags & LAN7500) ?
mue_csr_write(un, MUE_FLOW, 0);
mue_csr_write(un, MUE_RX_ADDRL, lo);
mue_csr_write(un, MUE_RX_ADDRH, hi);
static int mue_csr_write(struct usbnet *, uint32_t, uint32_t);