sys/arch/hpcmips/dev/mq200machdep.c

219

mq200_write(sc, ops[0], ops[1]);

sys/arch/hpcmips/dev/mq200machdep.c

223

mq200_write(sc, ops[0], reg);

sys/arch/hpcmips/dev/mq200machdep.c

242

mq200_write(sc, ops[1], accum);

sys/arch/hpcmips/dev/mq200machdep.c

246

mq200_write(sc, ops[1], reg);

sys/arch/hpcmips/dev/mq200priv.h

112

mq200_write(struct mq200_softc *sc, int offset, u_int32_t data);

sys/arch/hpcmips/dev/mq200subr.c

228

mq200_write(sc, MQ200_GC1CRTCR, 0);

sys/arch/hpcmips/dev/mq200subr.c

265

mq200_write(sc, MQ200_GCHDCR(MQ200_GC1),

sys/arch/hpcmips/dev/mq200subr.c

270

mq200_write(sc, MQ200_GCVDCR(MQ200_GC1),

sys/arch/hpcmips/dev/mq200subr.c

275

mq200_write(sc, MQ200_GCHSCR(MQ200_GC1),

sys/arch/hpcmips/dev/mq200subr.c

280

mq200_write(sc, MQ200_GCVSCR(MQ200_GC1),

sys/arch/hpcmips/dev/mq200subr.c

293

mq200_write(sc, MQ200_GC1CRTCR,

sys/arch/hpcmips/dev/mq200subr.c

364

mq200_write(sc, MQ200_GCWHCR(gc),

sys/arch/hpcmips/dev/mq200subr.c

369

mq200_write(sc, MQ200_GCWVCR(gc),