sys/arch/hpcmips/dev/mq200.c

128

regval = mq200_read(sc, MQ200_PC08R);

sys/arch/hpcmips/dev/mq200debug.c

110

reg = mq200_read(sc, MQ200_PLL3R);

sys/arch/hpcmips/dev/mq200debug.c

131

reg = mq200_read(sc, MQ200_GCCR(MQ200_GC1));

sys/arch/hpcmips/dev/mq200debug.c

141

reg = mq200_read(sc, MQ200_GC1CRTCR);

sys/arch/hpcmips/dev/mq200debug.c

144

reg = mq200_read(sc, MQ200_FPCR);

sys/arch/hpcmips/dev/mq200debug.c

153

reg = mq200_read(sc, MQ200_GCCR(MQ200_GC2));

sys/arch/hpcmips/dev/mq200debug.c

162

reg = mq200_read(sc, MQ200_FPCR);

sys/arch/hpcmips/dev/mq200debug.c

213

mq200_read(sc, regs[i].base + (j * 4)));

sys/arch/hpcmips/dev/mq200debug.c

260

reg = mq200_read(sc, MQ200_GCCR(gc));

sys/arch/hpcmips/dev/mq200debug.c

284

reg = mq200_read(sc, MQ200_GC1CRTCR);

sys/arch/hpcmips/dev/mq200debug.c

361

reg = mq200_read(sc, MQ200_GCHDCR(gc));

sys/arch/hpcmips/dev/mq200debug.c

374

reg = mq200_read(sc, MQ200_GCVDCR(gc));

sys/arch/hpcmips/dev/mq200debug.c

387

reg = mq200_read(sc, MQ200_GCHSCR(gc));

sys/arch/hpcmips/dev/mq200debug.c

395

reg = mq200_read(sc, MQ200_GCVSCR(gc));

sys/arch/hpcmips/dev/mq200debug.c

404

reg = mq200_read(sc, MQ200_GC1VDCNTR);

sys/arch/hpcmips/dev/mq200debug.c

412

reg = mq200_read(sc, MQ200_GCWHCR(gc));

sys/arch/hpcmips/dev/mq200debug.c

426

reg = mq200_read(sc, MQ200_GCWVCR(gc));

sys/arch/hpcmips/dev/mq200debug.c

435

reg = mq200_read(sc, MQ200_GCAWHCR(gc));

sys/arch/hpcmips/dev/mq200debug.c

449

reg = mq200_read(sc, MQ200_GCAWVCR(gc));

sys/arch/hpcmips/dev/mq200debug.c

458

reg = mq200_read(sc, MQ200_GCWSAR(gc));

sys/arch/hpcmips/dev/mq200debug.c

465

reg = mq200_read(sc, MQ200_GCAWSAR(gc));

sys/arch/hpcmips/dev/mq200debug.c

473

reg = mq200_read(sc, MQ200_GCWSTR(gc));

sys/arch/hpcmips/dev/mq200debug.c

482

reg = mq200_read(sc, MQ200_GCHCPR(gc));

sys/arch/hpcmips/dev/mq200debug.c

491

reg = mq200_read(sc, MQ200_GCHCAOR(gc));

sys/arch/hpcmips/dev/mq200debug.c

498

reg = mq200_read(sc, MQ200_GCHCFCR(gc));

sys/arch/hpcmips/dev/mq200debug.c

504

reg = mq200_read(sc, MQ200_GCHCBCR(gc));

sys/arch/hpcmips/dev/mq200debug.c

531

reg = mq200_read(sc, MQ200_FPCR);

sys/arch/hpcmips/dev/mq200debug.c

537

reg = mq200_read(sc, MQ200_FPPCR);

sys/arch/hpcmips/dev/mq200debug.c

72

pm00r = mq200_read(sc, MQ200_PMCR);

sys/arch/hpcmips/dev/mq200debug.c

76

reg = mq200_read(sc, MQ200_MMR(1));

sys/arch/hpcmips/dev/mq200debug.c

83

reg = mq200_read(sc, MQ200_DCMISCR);

sys/arch/hpcmips/dev/mq200debug.c

95

reg = mq200_read(sc, MQ200_PLL2R);

sys/arch/hpcmips/dev/mq200machdep.c

221

reg = mq200_read(sc, ops[0]);

sys/arch/hpcmips/dev/mq200machdep.c

237

reg = mq200_read(sc, ops[1]);

sys/arch/hpcmips/dev/mq200machdep.c

244

reg = mq200_read(sc, ops[1]);

sys/arch/hpcmips/dev/mq200subr.c

232

while (mq200_read(sc, MQ200_PMCR) & MQ200_PMC_SEQPROGRESS)

sys/arch/hpcmips/dev/mq200subr.c

303

while (mq200_read(sc, MQ200_PMCR) & MQ200_PMC_SEQPROGRESS)

sys/arch/hpcmips/dev/mq200subr.c

319

while (mq200_read(sc, MQ200_PMCR) & MQ200_PMC_SEQPROGRESS)