mfdcr
mtdcr(DCR_CPC0_CR1, mfdcr(DCR_CPC0_CR1) & ~CPC0_CR1_CETE);
val = mfdcr(DCR_SDRAM0_CFGDATA);
br[0] = mfdcr(DCR_BR4);
br[1] = mfdcr(DCR_BR5);
br[2] = mfdcr(DCR_BR6);
br[3] = mfdcr(DCR_BR7);
mtdcr(DCR_CPC0_CR1, mfdcr(DCR_CPC0_CR1) & ~CPC0_CR1_CETE);
pllmode = mfdcr(DCR_CPC0_PLLMR);
psr = mfdcr(DCR_CPC0_PSR);
mtdcr(DCR_CPC0_CR1, mfdcr(DCR_CPC0_CR1) & ~CPC0_CR1_CETE);
mtdcr(DCR_CPC0_CR1, mfdcr(DCR_CPC0_CR1) & ~CPC0_CR1_CETE);
mfdcr(DCR_UIC1_BASE + DCR_UIC_PR) & ~0x80000000);
mfdcr(DCR_UIC1_BASE + DCR_UIC_TR) & ~0x80000000);
mfdcr(DCR_UIC3_BASE + DCR_UIC_PR) & ~0x000ff000);
mfdcr(DCR_UIC3_BASE + DCR_UIC_TR) & ~0x000ff000);
uint32_t cr = mfdcr(DCR_AHB_CR);
mfdcr(DCR_AHB_REV), mfdcr(DCR_AHB_TOP), mfdcr(DCR_AHB_BOT),
mfdcr(DCR_AHB_ATT), cr,
(unsigned int)mfdcr((base) + DCR_UIC_SR), \
(unsigned int)mfdcr((base) + DCR_UIC_MSR), \
(unsigned int)mfdcr((base) + DCR_UIC_ER), \
(unsigned int)mfdcr((base) + DCR_UIC_PR), \
(unsigned int)mfdcr((base) + DCR_UIC_TR))
case (addr): val = mfdcr((base) + (addr) / 4); break
#define mfidcr(addr) mfdcr(IDCR_BASE + (addr))
mtdcr(DCR_CPC0_CR1, mfdcr(DCR_CPC0_CR1) & ~CPC0_CR1_CETE);
mfdcr(DCR_PLB4A0_ACR), mfdcr(DCR_PLB4A1_ACR),
esr = mfdcr(DCR_SDRAM0_CFGDATA);
ear = mfdcr(DCR_SDRAM0_CFGDATA);
esr = mfdcr(DCR_SDRAM0_CFGDATA);
esr = mfdcr(DCR_SDRAM0_CFGDATA);
ebc0_bNcr = mfdcr(DCR_EBC0_CFGDATA);
while ((tcei = mfdcr(DCR_MAL0_TXEOBISR))) {
while ((rcei = mfdcr(DCR_MAL0_RXEOBISR))) {
while ((txde = mfdcr(DCR_MAL0_TXDEIR))) {
while ((rxde = mfdcr(DCR_MAL0_RXDEIR))) {
esr = mfdcr(DCR_MAL0_ESR);
while (mfdcr(DCR_MAL0_CFG) & MAL0_CFG_SR) {
pllmr = mfdcr(DCR_CPC0_PLLMR);
while ((mfdcr(DCR_L2C0_SR) & L2C_SR_CC) == 0)
while ((mfdcr(DCR_L2C0_SR) & L2C_SR_CC) == 0)
while ((mfdcr(DCR_L2C0_SR) & L2C_SR_CC) == 0)
while ((mfdcr(DCR_L2C0_SR) & L2C_SR_CC) == 0)
ibm4xx_460ex_l2_cfg = mfdcr(DCR_L2C0_CFG);
while ((mfdcr(DCR_L2C0_SR) & L2C_SR_CC) == 0)
mfdcr((base) + PEGPL_CFG) & ~PEGPL_CFG_PLE); \
return mfdcr(DCR_EXISR);
return mfdcr(DCR_EXIER);
return mfdcr(DCR_UIC0_BASE + DCR_UIC_MSR);
return mfdcr(DCR_UIC0_BASE + DCR_UIC_ER);
return mfdcr(DCR_UIC1_BASE + DCR_UIC_MSR);
return mfdcr(DCR_UIC1_BASE + DCR_UIC_ER);
return mfdcr(DCR_UIC2_BASE + DCR_UIC_MSR);
return mfdcr(DCR_UIC2_BASE + DCR_UIC_ER);
return mfdcr(DCR_UIC3_BASE + DCR_UIC_MSR);
return mfdcr(DCR_UIC3_BASE + DCR_UIC_ER);
return mfdcr(DCR_CPR0_CFGDATA);
return mfdcr(DCR_SDR0_CFGDATA);