mesh_set_reg
mesh_set_reg(sc, MESH_SYNC_PARAM, 2);
mesh_set_reg(sc, MESH_SEQUENCE, MESH_CMD_BUSFREE);
static inline void mesh_set_reg(struct mesh_softc *, int, int);
mesh_set_reg(sc, MESH_XFER_COUNT0, count); \
mesh_set_reg(sc, MESH_XFER_COUNT1, count >> 8); \
mesh_set_reg(sc, MESH_SYNC_PARAM, 2);
mesh_set_reg(sc, MESH_INTERRUPT, intr);
mesh_set_reg(sc, MESH_SEQUENCE,
mesh_set_reg(sc, MESH_INTERRUPT, 7);
mesh_set_reg(sc, MESH_DEST_ID, sc->sc_id);
mesh_set_reg(sc, MESH_INTR_MASK, 0); /* disable intr. */
mesh_set_reg(sc, MESH_SEQUENCE, MESH_CMD_ARBITRATE);
mesh_set_reg(sc, MESH_INTERRUPT, 1);
mesh_set_reg(sc, MESH_INTR_MASK, 7);
mesh_set_reg(sc, MESH_DEST_ID, scb->target);
mesh_set_reg(sc, MESH_SEQUENCE, MESH_CMD_SELECT | MESH_SEQ_ATN);
mesh_set_reg(sc, MESH_SEQUENCE, MESH_CMD_FLUSH_FIFO);
mesh_set_reg(sc, MESH_SEQUENCE, MESH_CMD_FLUSH_FIFO);
mesh_set_reg(sc, MESH_SEQUENCE, MESH_CMD_COMMAND);
mesh_set_reg(sc, MESH_FIFO, *cmdp++);
mesh_set_reg(sc, MESH_SEQUENCE, MESH_CMD_DATAIN | MESH_SEQ_DMA);
mesh_set_reg(sc, MESH_SEQUENCE, MESH_CMD_DATAOUT | MESH_SEQ_DMA);
mesh_set_reg(sc, MESH_SEQUENCE, MESH_CMD_STATUS);
mesh_set_reg(sc, MESH_SEQUENCE, MESH_CMD_FLUSH_FIFO);
mesh_set_reg(sc, MESH_SEQUENCE, MESH_CMD_MSGIN);
mesh_set_reg(sc, MESH_SEQUENCE, MESH_CMD_MSGIN);
mesh_set_reg(sc, MESH_SEQUENCE, MESH_CMD_MSGIN);
mesh_set_reg(sc, MESH_SEQUENCE, MESH_CMD_BUSFREE);
mesh_set_reg(sc, MESH_SEQUENCE, MESH_CMD_BUSFREE); /* XXX really? */
mesh_set_reg(sc, MESH_SEQUENCE, MESH_CMD_MSGOUT);
mesh_set_reg(sc, MESH_FIFO, sc->sc_omsg[0]);
mesh_set_reg(sc, MESH_SEQUENCE, MESH_CMD_MSGOUT | MESH_SEQ_ATN);
mesh_set_reg(sc, MESH_FIFO, sc->sc_omsg[i]);
mesh_set_reg(sc, MESH_FIFO, sc->sc_omsg[i]);
mesh_set_reg(sc, MESH_INTR_MASK, 0);
mesh_set_reg(sc, MESH_BUS_STATUS1, MESH_STATUS1_RST);
mesh_set_reg(sc, MESH_BUS_STATUS1, 0);
mesh_set_reg(sc, MESH_INTR_MASK, 0);
mesh_set_reg(sc, MESH_SEQUENCE, MESH_CMD_RESET_MESH);
mesh_set_reg(sc, MESH_INTERRUPT, 0x7);
mesh_set_reg(sc, MESH_SOURCE_ID, sc->sc_id);
mesh_set_reg(sc, MESH_SYNC_PARAM, 2);
mesh_set_reg(sc, MESH_SEL_TIMEOUT, 250 * sc->sc_freq / 500);
mesh_set_reg(sc, MESH_SEQUENCE, MESH_CMD_ENABLE_PARITY);
mesh_set_reg(sc, MESH_INTR_MASK, 0x7);
mesh_set_reg(sc, MESH_SYNC_PARAM, 2);
mesh_set_reg(sc, MESH_SYNC_PARAM, (offset << 4) | v);