link_status
static void link_status(prop_dictionary_t, prop_dictionary_t, bool);
.af_name = "link", .af_af = AF_LINK, .af_status = link_status,
uint8_t link_status[DP_LINK_STATUS_SIZE];
drm_dp_dpcd_read_link_status(&sc->sc_dpaux, link_status)) {
if (!drm_dp_clock_recovery_ok(link_status, link->num_lanes)) {
vs = drm_dp_get_adjust_request_voltage(link_status, i);
pe = drm_dp_get_adjust_request_pre_emphasis(link_status, i);
uint8_t link_status[DP_LINK_STATUS_SIZE];
drm_dp_dpcd_read_link_status(&sc->sc_dpaux, link_status)) {
if (!drm_dp_channel_eq_ok(link_status, link->num_lanes)) {
vs = drm_dp_get_adjust_request_voltage(link_status, i);
pe = drm_dp_get_adjust_request_pre_emphasis(link_status, i);
void t3_os_link_changed(adapter_t *adapter, int port_id, int link_status,
t3_os_link_changed(adapter_t *adapter, int port_id, int link_status, int speed,
if (link_status) {
pcireg_t link_status = pci_conf_read(pa->pa_pc, pa->pa_tag,
"0x%08X\n", link_status);
sc->link_speed = (link_status & PCIE_LCSR_LINKSPEED) >> 16;
sc->link_width = (link_status & PCIE_LCSR_NLW) >> 20;
if (event->link_status) {
uint8_t link_status;
void ixgbe_set_pci_config_data_generic(struct ixgbe_hw *hw, u16 link_status)
switch (link_status & IXGBE_PCI_LINK_WIDTH) {
switch (link_status & IXGBE_PCI_LINK_SPEED) {
u16 link_status;
link_status = IXGBE_READ_PCIE_WORD(hw, IXGBE_PCI_LINK_STATUS);
ixgbe_set_pci_config_data_generic(hw, link_status);
void ixgbe_set_pci_config_data_generic(struct ixgbe_hw *hw, u16 link_status);