sys/arch/mips/alchemy/dev/com_aubus.c

185

[COM_REG_MCR] = AUCOM_MCR,

sys/arch/mips/cavium/dev/octeon_uart.c

81

[COM_REG_MCR] = MIO_UART_MCR_OFFSET,

sys/arch/mips/ralink/ralink_com.c

382

[COM_REG_MCR] = RA_UART_MCR,

sys/dev/ic/com.c

1953

CSR_WRITE_1(regsp, COM_REG_MCR, sc->sc_mcr_active = sc->sc_mcr);

sys/dev/ic/com.c

1979

CSR_WRITE_1(regsp, COM_REG_MCR, sc->sc_mcr | MCR_TCR_TLR);

sys/dev/ic/com.c

1986

CSR_WRITE_1(regsp, COM_REG_MCR, sc->sc_mcr);

sys/dev/ic/com.c

2063

CSR_WRITE_1(regsp, COM_REG_MCR, sc->sc_mcr_active);

sys/dev/ic/com.c

274

[COM_REG_MCR] = com_mcr,

sys/dev/ic/com.c

2809

CSR_WRITE_1(regsp, COM_REG_MCR, MCR_DTR | MCR_RTS);

sys/dev/ic/com.c

2833

CSR_WRITE_1(regsp, COM_REG_MCR, MCR_DTR | MCR_RTS | MCR_TCR_TLR);

sys/dev/ic/com.c

2840

CSR_WRITE_1(regsp, COM_REG_MCR, MCR_DTR | MCR_RTS);

sys/dev/ic/com.c

554

CSR_WRITE_1(&sc->sc_regs, COM_REG_MCR, sc->sc_mcr);