sys/arch/evbarm/gemini/gemini_machdep.c

501

while ((com0addr[COM_REG_LSR * 4] & LSR_TXRDY) == 0)

sys/arch/evbarm/gemini/gemini_machdep.c

507

while ((com0addr[COM_REG_LSR * 4] & LSR_TSRE) == 0)

sys/arch/mips/alchemy/dev/com_aubus.c

186

[COM_REG_LSR] = AUCOM_LSR,

sys/arch/mips/cavium/dev/octeon_uart.c

82

[COM_REG_LSR] = MIO_UART_LSR_OFFSET,

sys/arch/mips/ralink/ralink_com.c

383

[COM_REG_LSR] = RA_UART_LSR,

sys/dev/ic/com.c

1883

while (ISSET(CSR_READ_1(regsp, COM_REG_LSR), LSR_RXRDY)

sys/dev/ic/com.c

2483

lsr = CSR_READ_1(regsp, COM_REG_LSR);

sys/dev/ic/com.c

2517

lsr = CSR_READ_1(regsp, COM_REG_LSR);

sys/dev/ic/com.c

2629

lsr = CSR_READ_1(regsp, COM_REG_LSR);

sys/dev/ic/com.c

2733

if (!ISSET(stat = CSR_READ_1(regsp, COM_REG_LSR), LSR_RXRDY)) {

sys/dev/ic/com.c

275

[COM_REG_LSR] = com_lsr,

sys/dev/ic/com.c

2756

&& ISSET(stat = CSR_READ_1(regsp, COM_REG_LSR), LSR_RXRDY)) {

sys/dev/ic/com.c

2766

while (!ISSET(CSR_READ_1(regsp, COM_REG_LSR), LSR_TXRDY) && --timo)