sys/arch/mips/alchemy/dev/com_aubus.c

184

[COM_REG_LCR] = AUCOM_LCTL,

sys/arch/mips/cavium/dev/octeon_uart.c

80

[COM_REG_LCR] = MIO_UART_LCR_OFFSET,

sys/arch/mips/ralink/ralink_com.c

381

[COM_REG_LCR] = RA_UART_LCR,

sys/dev/ic/com.c

1935

CSR_WRITE_1(regsp, COM_REG_LCR, LCR_EERS);

sys/dev/ic/com.c

1940

CSR_WRITE_1(regsp, COM_REG_LCR, LCR_EERS);

sys/dev/ic/com.c

1948

CSR_WRITE_1(regsp, COM_REG_LCR, sc->sc_lcr | LCR_DLAB);

sys/dev/ic/com.c

1952

CSR_WRITE_1(regsp, COM_REG_LCR, sc->sc_lcr);

sys/dev/ic/com.c

1957

CSR_WRITE_1(regsp, COM_REG_LCR, LCR_EERS);

sys/dev/ic/com.c

1959

CSR_WRITE_1(regsp, COM_REG_LCR, sc->sc_lcr);

sys/dev/ic/com.c

2421

CSR_WRITE_1(regsp, COM_REG_LCR, sc->sc_lcr);

sys/dev/ic/com.c

2432

CSR_WRITE_1(regsp, COM_REG_LCR, sc->sc_lcr | LCR_DLAB);

sys/dev/ic/com.c

2435

CSR_WRITE_1(regsp, COM_REG_LCR, sc->sc_lcr);

sys/dev/ic/com.c

2457

CSR_WRITE_1(regsp, COM_REG_LCR, sc->sc_lcr | LCR_DLAB);

sys/dev/ic/com.c

2460

CSR_WRITE_1(regsp, COM_REG_LCR, sc->sc_lcr);

sys/dev/ic/com.c

273

[COM_REG_LCR] = com_lcr,

sys/dev/ic/com.c

2800

CSR_WRITE_1(regsp, COM_REG_LCR, LCR_EERS);

sys/dev/ic/com.c

2803

CSR_WRITE_1(regsp, COM_REG_LCR, LCR_DLAB);

sys/dev/ic/com.c

2808

CSR_WRITE_1(regsp, COM_REG_LCR, cflag2lcr(cflag));

sys/dev/ic/com.c

518

CSR_WRITE_1(regs, COM_REG_LCR, LCR_8BITS);

sys/dev/ic/com.c

520

if ((CSR_READ_1(regs, COM_REG_LCR) != LCR_8BITS) ||

sys/dev/ic/com.c

755

lcr = CSR_READ_1(regsp, COM_REG_LCR);

sys/dev/ic/com.c

756

CSR_WRITE_1(regsp, COM_REG_LCR, LCR_EERS);

sys/dev/ic/com.c

759

CSR_WRITE_1(regsp, COM_REG_LCR,

sys/dev/ic/com.c

771

CSR_WRITE_1(regsp, COM_REG_LCR, lcr);

sys/dev/ic/com.c

793

lcr = CSR_READ_1(regsp, COM_REG_LCR);

sys/dev/ic/com.c

794

CSR_WRITE_1(regsp, COM_REG_LCR,

sys/dev/ic/com.c

800

CSR_WRITE_1(regsp, COM_REG_LCR, lcr | LCR_DLAB);

sys/dev/ic/com.c

805

CSR_WRITE_1(regsp, COM_REG_LCR, lcr);