sys/arch/mips/alchemy/dev/com_aubus.c

181

[COM_REG_IIR] = AUCOM_IIR,

sys/arch/mips/cavium/dev/octeon_uart.c

77

[COM_REG_IIR] = MIO_UART_IIR_OFFSET,

sys/arch/mips/ralink/ralink_com.c

378

[COM_REG_IIR] = RA_UART_IIR,

sys/dev/ic/com.c

2396

iir = CSR_READ_1(regsp, COM_REG_IIR);

sys/dev/ic/com.c

2422

iir = CSR_READ_1(regsp, COM_REG_IIR);

sys/dev/ic/com.c

2616

CSR_READ_1(regsp, COM_REG_IIR)), IIR_NOPEND) &&

sys/dev/ic/com.c

2676

if (!ISSET((iir = CSR_READ_1(regsp, COM_REG_IIR)), IIR_NOPEND))

sys/dev/ic/com.c

268

[COM_REG_IIR] = com_iir,

sys/dev/ic/com.c

2739

stat = CSR_READ_1(regsp, COM_REG_IIR);

sys/dev/ic/com.c

2759

stat = CSR_READ_1(regsp, COM_REG_IIR);

sys/dev/ic/com.c

3045

(void)CSR_READ_1(&sc->sc_regs, COM_REG_IIR);

sys/dev/ic/com.c

519

CSR_WRITE_1(regs, COM_REG_IIR, 0);

sys/dev/ic/com.c

521

(CSR_READ_1(regs, COM_REG_IIR) & 0x38))

sys/dev/ic/com.c

734

if (ISSET(CSR_READ_1(regsp, COM_REG_IIR), IIR_FIFO_MASK)

sys/dev/ic/com.c

798

iir1 = CSR_READ_1(regsp, COM_REG_IIR);

sys/dev/ic/com.c

803

iir2 = CSR_READ_1(regsp, COM_REG_IIR);

sys/dev/ic/com.c

952

(void) CSR_READ_1(regsp, COM_REG_IIR);