sys/arch/mips/alchemy/dev/com_aubus.c

182

[COM_REG_FIFO] = AUCOM_FIFO,

sys/arch/mips/cavium/dev/octeon_uart.c

78

[COM_REG_FIFO] = MIO_UART_FCR_OFFSET,

sys/arch/mips/ralink/ralink_com.c

379

[COM_REG_FIFO] = RA_UART_FCR,

sys/dev/ic/com.c

1904

fifo = CSR_READ_1(regsp, COM_REG_FIFO) & (FIFO_TRIGGER_1 |

sys/dev/ic/com.c

1906

CSR_WRITE_1(regsp, COM_REG_FIFO,

sys/dev/ic/com.c

1954

CSR_WRITE_1(regsp, COM_REG_FIFO, sc->sc_fifo);

sys/dev/ic/com.c

269

[COM_REG_FIFO] = com_fifo,

sys/dev/ic/com.c

2812

CSR_WRITE_1(regsp, COM_REG_FIFO,

sys/dev/ic/com.c

2816

CSR_WRITE_1(regsp, COM_REG_FIFO,

sys/dev/ic/com.c

3034

CSR_WRITE_1(&sc->sc_regs, COM_REG_FIFO, 0);

sys/dev/ic/com.c

683

CSR_WRITE_1(regsp, COM_REG_FIFO,

sys/dev/ic/com.c

691

CSR_WRITE_1(regsp, COM_REG_FIFO,

sys/dev/ic/com.c

704

CSR_WRITE_1(regsp, COM_REG_FIFO, 0);

sys/dev/ic/com.c

708

CSR_WRITE_1(regsp, COM_REG_FIFO,

sys/dev/ic/com.c

719

CSR_WRITE_1(regsp, COM_REG_FIFO,

sys/dev/ic/com.c

727

CSR_WRITE_1(regsp, COM_REG_FIFO,

sys/dev/ic/com.c

731

CSR_WRITE_1(regsp, COM_REG_FIFO,

sys/dev/ic/com.c

736

if (ISSET(CSR_READ_1(regsp, COM_REG_FIFO), FIFO_TRIGGER_14)

sys/dev/ic/com.c

796

CSR_WRITE_1(regsp, COM_REG_FIFO,

sys/dev/ic/com.c

799

CSR_WRITE_1(regsp, COM_REG_FIFO, fcr);

sys/dev/ic/com.c

801

CSR_WRITE_1(regsp, COM_REG_FIFO,

sys/dev/ic/com.c

813

CSR_WRITE_1(regsp, COM_REG_FIFO, fcr);

sys/dev/ic/com.c

824

CSR_WRITE_1(regsp, COM_REG_FIFO, 0);