sys/arch/mips/alchemy/dev/com_aubus.c

178

[COM_REG_DLBL] = AUCOM_DLB,

sys/arch/mips/cavium/dev/octeon_uart.c

74

[COM_REG_DLBL] = MIO_UART_DLL_OFFSET,

sys/arch/mips/ralink/ralink_com.c

373

[COM_REG_DLBL] = RA_UART_DLL,

sys/dev/ic/com.c

1945

CSR_WRITE_2(regsp, COM_REG_DLBL, sc->sc_dlbl +

sys/dev/ic/com.c

1949

CSR_WRITE_1(regsp, COM_REG_DLBL, sc->sc_dlbl);

sys/dev/ic/com.c

2433

CSR_WRITE_1(regsp, COM_REG_DLBL, sc->sc_dlbl);

sys/dev/ic/com.c

2458

CSR_WRITE_1(regsp, COM_REG_DLBL, sc->sc_dlbl);

sys/dev/ic/com.c

265

[COM_REG_DLBL] = com_dlbl,

sys/dev/ic/com.c

2796

CSR_WRITE_2(regsp, COM_REG_DLBL, rate);

sys/dev/ic/com.c

2804

CSR_WRITE_1(regsp, COM_REG_DLBL, rate & 0xff);