sys/arch/mips/alchemy/dev/com_aubus.c

179

[COM_REG_DLBH] = AUCOM_DLB,

sys/arch/mips/cavium/dev/octeon_uart.c

75

[COM_REG_DLBH] = MIO_UART_DLH_OFFSET,

sys/arch/mips/ralink/ralink_com.c

375

[COM_REG_DLBH] = RA_UART_DLM,

sys/dev/ic/com.c

1950

CSR_WRITE_1(regsp, COM_REG_DLBH, sc->sc_dlbh);

sys/dev/ic/com.c

2434

CSR_WRITE_1(regsp, COM_REG_DLBH, sc->sc_dlbh);

sys/dev/ic/com.c

2459

CSR_WRITE_1(regsp, COM_REG_DLBH, sc->sc_dlbh);

sys/dev/ic/com.c

266

[COM_REG_DLBH] = com_dlbh,

sys/dev/ic/com.c

2805

CSR_WRITE_1(regsp, COM_REG_DLBH, rate >> 8);