sys/arch/arm/cortex/gic.c

206

gicd_write(sc, GICD_ISENABLERn(group), irq_mask);

sys/arch/arm/cortex/gic.c

218

gicd_write(sc, GICD_ICENABLERn(group), irq_mask);

sys/arch/arm/cortex/gic.c

288

gicd_write(sc, targets_reg, targets);

sys/arch/arm/cortex/gic.c

312

gicd_write(&armgic_softc, GICD_SGIR, machdep);

sys/arch/arm/cortex/gic.c

449

gicd_write(sc, targets_reg, targets);

sys/arch/arm/cortex/gic.c

462

gicd_write(sc, cfg_reg, new_cfg);

sys/arch/arm/cortex/gic.c

483

gicd_write(sc, priority_reg, priority);

sys/arch/arm/cortex/gic.c

493

gicd_write(sc, priority_reg, ~0);

sys/arch/arm/cortex/gic.c

514

gicd_write(sc, priority_reg, priority);

sys/arch/arm/cortex/gic.c

535

gicd_write(sc, targets_reg, targets);

sys/arch/arm/cortex/gic.c

554

gicd_write(sc, GICD_ISENABLERn(0),

sys/arch/arm/cortex/gic.c

591

gicd_write(sc, GICD_SGIR, sgir);

sys/arch/arm/cortex/gic.c

625

gicd_write(sc, GICD_CTRL, 0); /* disable all interrupts */

sys/arch/arm/cortex/gic.c

653

gicd_write(sc, GICD_ISENABLERn(group), 0xffffffff);

sys/arch/arm/cortex/gic.c

659

gicd_write(sc, GICD_ICENABLERn(group), valid);

sys/arch/arm/cortex/gic.c

686

gicd_write(sc, GICD_CTRL, GICD_CTRL_Enable); // enable Distributer