sys/arch/arm/cortex/gic.c

231

gicc_write(sc, GICC_PMR, armgic_ipl_to_priority(ipl));

sys/arch/arm/cortex/gic.c

336

gicc_write(sc, GICC_PMR, armgic_ipl_to_priority(old_ipl));

sys/arch/arm/cortex/gic.c

390

gicc_write(sc, GICC_PMR, armgic_ipl_to_priority(ipl));

sys/arch/arm/cortex/gic.c

396

gicc_write(sc, GICC_EOIR, iar);

sys/arch/arm/cortex/gic.c

559

gicc_write(sc, GICC_PMR, armgic_ipl_to_priority(ci->ci_cpl)); // set PMR

sys/arch/arm/cortex/gic.c

560

gicc_write(sc, GICC_CTRL, GICC_CTRL_V1_Enable); // enable interrupt

sys/arch/arm/cortex/gic.c

624

gicc_write(sc, GICC_CTRL, 0); /* disable all interrupts */

sys/arch/arm/cortex/gic.c

627

gicc_write(sc, GICC_PMR, 0xff);

sys/arch/arm/cortex/gic.c

687

gicc_write(sc, GICC_CTRL, GICC_CTRL_V1_Enable); // enable CPU interrupts