CLK_READ
uint32_t cntl0 = CLK_READ(sc, HHI_SYS_CPU_CLK_CNTL0);
uint32_t cntl = CLK_READ(sc, HHI_SYS_PLL_CNTL);
} while ((CLK_READ(sc, HHI_SYS_PLL_CNTL) & HHI_SYS_PLL_CNTL_LOCK) == 0);
const uint32_t val = CLK_READ(sc, reset->reg);
const uint32_t val = CLK_READ(sc, reset->reg);
uint32_t _cwb_tmp_ = CLK_READ((sc), (reg)); \
val = CLK_READ(sc, div->reg);
val = CLK_READ(sc, div->reg);
val = CLK_READ(sc, gate->reg);
val = CLK_READ(sc, mpll->sdm.reg);
val = CLK_READ(sc, mpll->n2.reg);
val = CLK_READ(sc, mux->reg);
val = CLK_READ(sc, pll->n.reg);
val = CLK_READ(sc, pll->m.reg);
val = CLK_READ(sc, pll->frac.reg);
if ((CLK_READ(sc, pll->l.reg) & pll->l.mask) != 0)
if ((CLK_READ(sc, clk->u.mux.reg) & __BIT(11)) == 0) {
val = CLK_READ(sc, reg_cntl0);
val = CLK_READ(sc, clk->u.mux.reg);
val = CLK_READ(sc, reg_cntl0);
val = CLK_READ(sc, reg_cntl0);
val = CLK_READ(sc, reg_cntl0);
val = CLK_READ(sc, reg_cntl0);
val = CLK_READ(sc, reg_cntl0);
val = CLK_READ(sc, reg_cntl0);
if ((CLK_READ(sc, reg_cntl0) & MESON_PLL_CNTL_REG_LOCK) != 0) {
val = CLK_READ(sc, clk->u.mux.reg);
cl->cl_csr |= CLK_READ; /* enable read (stop time) */
cl->cl_csr &= ~CLK_READ; /* time wears on */