CLK_GATE_SIMPLE
CLK_GATE_SIMPLE("cml0", "pll_e",
CLK_GATE_SIMPLE("cml1", "pll_e",
CLK_GATE_SIMPLE("pll_p_out5", "div_pll_p_out5",
CLK_GATE_SIMPLE("PLL_U_OUT1", "DIV_PLL_U_OUT1",
CLK_GATE_SIMPLE("PLL_U_OUT2", "DIV_PLL_U_OUT2",
CLK_GATE_SIMPLE("CML0", "PLL_E",
CLK_GATE_SIMPLE("CML1", "PLL_E",