CLK_DIV
CLK_DIV("div_uarta", "mux_uarta",
CLK_DIV("div_uartb", "mux_uartb",
CLK_DIV("div_uartc", "mux_uartc",
CLK_DIV("div_uartd", "mux_uartd",
CLK_DIV("div_sdmmc1", "mux_sdmmc1",
CLK_DIV("div_sdmmc2", "mux_sdmmc2",
CLK_DIV("div_sdmmc3", "mux_sdmmc3",
CLK_DIV("div_sdmmc4", "mux_sdmmc4",
CLK_DIV("div_i2c1", "mux_i2c1",
CLK_DIV("div_i2c2", "mux_i2c2",
CLK_DIV("div_i2c3", "mux_i2c3",
CLK_DIV("div_i2c4", "mux_i2c4",
CLK_DIV("div_i2c5", "mux_i2c5",
CLK_DIV("div_i2c6", "mux_i2c6",
CLK_DIV("div_spi1", "mux_spi1",
CLK_DIV("div_spi2", "mux_spi2",
CLK_DIV("div_spi3", "mux_spi3",
CLK_DIV("div_spi4", "mux_spi4",
CLK_DIV("div_spi5", "mux_spi5",
CLK_DIV("div_spi6", "mux_spi6",
CLK_DIV("div_sata_oob", "mux_sata_oob",
CLK_DIV("div_sata", "mux_sata",
CLK_DIV("div_hda2codec_2x", "mux_hda2codec_2x",
CLK_DIV("div_hda", "mux_hda",
CLK_DIV("div_soc_therm", "mux_soc_therm",
CLK_DIV("div_mselect", "mux_mselect",
CLK_DIV("div_tsensor", "mux_tsensor",
CLK_DIV("div_host1x", "mux_host1x",
CLK_DIV("div_hdmi", "mux_hdmi",
CLK_DIV("div_pll_p_out5", "pll_p",
CLK_DIV("xusb_host_src", "mux_xusb_host",
CLK_DIV("xusb_ss_src", "mux_xusb_ss",
CLK_DIV("xusb_fs_src", "mux_xusb_fs",
CLK_DIV("xusb_falcon_src", "mux_xusb_falcon",
CLK_DIV("DIV_UARTA", "MUX_UARTA",
CLK_DIV("DIV_UARTB", "MUX_UARTB",
CLK_DIV("DIV_UARTC", "MUX_UARTC",
CLK_DIV("DIV_UARTD", "MUX_UARTD",
CLK_DIV("DIV_SDMMC1", "MUX_SDMMC1",
CLK_DIV("DIV_SDMMC2", "MUX_SDMMC2",
CLK_DIV("DIV_SDMMC3", "MUX_SDMMC3",
CLK_DIV("DIV_SDMMC4", "MUX_SDMMC4",
CLK_DIV("DIV_I2C1", "MUX_I2C1",
CLK_DIV("DIV_I2C2", "MUX_I2C2",
CLK_DIV("DIV_I2C3", "MUX_I2C3",
CLK_DIV("DIV_I2C4", "MUX_I2C4",
CLK_DIV("DIV_I2C5", "MUX_I2C5",
CLK_DIV("DIV_I2C6", "MUX_I2C6",
CLK_DIV("XUSB_HOST_SRC", "MUX_XUSB_HOST",
CLK_DIV("XUSB_SS_SRC", "MUX_XUSB_SS",
CLK_DIV("XUSB_FS_SRC", "MUX_XUSB_FS",
CLK_DIV("XUSB_FALCON_SRC", "MUX_XUSB_FALCON",
CLK_DIV("USB2_HSIC_TRK", "CLK_M",
CLK_DIV("DIV_PLL_U_OUT1", "PLL_U",
CLK_DIV("DIV_PLL_U_OUT2", "PLL_U",
CLK_DIV("DIV_MSELECT", "MUX_MSELECT",
CLK_DIV("DIV_TSENSOR", "MUX_TSENSOR",
CLK_DIV("DIV_SOC_THERM", "MUX_SOC_THERM",
CLK_DIV("DIV_HDA2CODEC_2X", "MUX_HDA2CODEC_2X",
CLK_DIV("DIV_HDA", "MUX_HDA",
CLK_DIV("DIV_SATA_OOB", "MUX_SATA_OOB",
CLK_DIV("DIV_SATA", "MUX_SATA",
CLK_DIV("periph_clk2", "periph_clk2_sel", CBCDR, PERIPH_CLK2_PODF),
CLK_DIV("periph2_clk2", "periph2_clk2_sel", CBCDR, PERIPH2_CLK2_PODF),
CLK_DIV("ipg", "ahb", CBCDR, IPG_PODF),
CLK_DIV("esai_pred", "esai_sel", CS1CDR, ESAI_CLK_PRED),
CLK_DIV("esai_podf", "esai_pred", CS1CDR, ESAI_CLK_PODF),
CLK_DIV("asrc_pred", "asrc_sel", CDCDR, SPDIF1_CLK_PRED),
CLK_DIV("asrc_podf", "asrc_pred", CDCDR, SPDIF1_CLK_PODF),
CLK_DIV("spdif_pred", "spdif_sel", CDCDR, SPDIF0_CLK_PRED),
CLK_DIV("spdif_podf", "spdif_pred", CDCDR, SPDIF0_CLK_PODF),
CLK_DIV("ecspi_root", "pll3_60m", CSCDR2, ECSPI_CLK_PODF),
CLK_DIV("can_root", "pll3_60m", CSCMR2, CAN_CLK_PODF),
CLK_DIV("uart_serial_podf", "pll3_80m", CSCDR1, UART_CLK_PODF),
CLK_DIV("gpu2d_core_podf", "gpu2d_core_sel", CBCMR, GPU2D_CORE_CLK_PODF),
CLK_DIV("gpu3d_core_podf", "gpu3d_core_sel", CBCMR, GPU3D_CORE_PODF),
CLK_DIV("gpu3d_shader", "gpu3d_shader_sel", CBCMR, GPU3D_SHADER_PODF),
CLK_DIV("ipu1_podf", "ipu1_sel", CSCDR3, IPU1_HSP_PODF),
CLK_DIV("ipu2_podf", "ipu2_sel", CSCDR3, IPU2_HSP_PODF),
CLK_DIV("ldb_di0_podf", "ldb_di0_div_3_5", CSCMR2, LDB_DI0_IPU_DIV),
CLK_DIV("ldb_di1_podf", "ldb_di1_div_3_5", CSCMR2, LDB_DI1_IPU_DIV),
CLK_DIV("ipu1_di0_pre", "ipu1_di0_pre_sel", CHSCCDR, IPU1_DI0_PODF),
CLK_DIV("ipu1_di1_pre", "ipu1_di1_pre_sel", CHSCCDR, IPU1_DI1_PODF),
CLK_DIV("ipu2_di0_pre", "ipu2_di0_pre_sel", CSCDR2, IPU2_DI0_PODF),
CLK_DIV("ipu2_di1_pre", "ipu2_di1_pre_sel", CSCDR2, IPU2_DI1_PODF),
CLK_DIV("hsi_tx_podf", "hsi_tx_sel", CDCDR, HSI_TX_PODF),
CLK_DIV("ssi1_pred", "ssi1_sel", CS1CDR, SSI1_CLK_PRED),
CLK_DIV("ssi1_podf", "ssi1_pred", CS1CDR, SSI1_CLK_PODF),
CLK_DIV("ssi2_pred", "ssi2_sel", CS2CDR, SSI2_CLK_PRED),
CLK_DIV("ssi2_podf", "ssi2_pred", CS2CDR, SSI2_CLK_PODF),
CLK_DIV("ssi3_pred", "ssi3_sel", CS1CDR, SSI3_CLK_PRED),
CLK_DIV("ssi3_podf", "ssi3_pred", CS1CDR, SSI3_CLK_PODF),
CLK_DIV("usdhc1_podf", "usdhc1_sel", CSCDR1, USDHC1_PODF),
CLK_DIV("usdhc2_podf", "usdhc2_sel", CSCDR1, USDHC2_PODF),
CLK_DIV("usdhc3_podf", "usdhc3_sel", CSCDR1, USDHC3_PODF),
CLK_DIV("usdhc4_podf", "usdhc4_sel", CSCDR1, USDHC4_PODF),
CLK_DIV("enfc_pred", "enfc_sel", CS2CDR, ENFC_CLK_PRED),
CLK_DIV("enfc_podf", "enfc_pred", CS2CDR, ENFC_CLK_PODF),
CLK_DIV("vpu_axi_podf", "vpu_axi_sel", CSCDR1, VPU_AXI_PODF),
CLK_DIV("cko1_podf", "cko1_sel", CCOSR, CLKO1_DIV),
CLK_DIV("cko2_podf", "cko2_sel", CCOSR, CLKO2_DIV),
CLK_DIV("ipg_per", "ipg", CSCMR1, PERCLK_PODF),
CLK_DIV("eim_podf", "eim_sel", CSCMR1, ACLK_PODF),
CLK_DIV("eim_slow_podf", "eim_slow_sel", CSCMR1, ACLK_EIM_SLOW_PODF),
CLK_DIV("periph_clk2", "periph_clk2_sel", CBCDR, PERIPH_CLK2_PODF),
CLK_DIV("periph2_clk2", "periph2_clk2_sel", CBCDR, PERIPH2_CLK2_PODF),
CLK_DIV("ipg", "ahb", CBCDR, IPG_PODF),
CLK_DIV("gpu_core_podf", "gpu_core_sel", CBCMR, GPU3D_SHADER_PODF),
CLK_DIV("gpu_axi_podf", "gpu_axi_sel", CBCMR, GPU3D_CORE_PODF),
CLK_DIV("lcdif1_podf", "lcdif1_pred", CBCMR, GPU2D_CORE_CLK_PODF),
CLK_DIV("esai_pred", "esai_sel", CS1CDR, ESAI_CLK_PRED),
CLK_DIV("esai_podf", "esai_pred", CS1CDR, ESAI_CLK_PODF),
CLK_DIV("spdif_pred", "spdif_sel", CDCDR, SPDIF0_CLK_PRED),
CLK_DIV("spdif_podf", "spdif_pred", CDCDR, SPDIF0_CLK_PODF),
CLK_DIV("audio_pred", "audio_sel", CDCDR, SPDIF1_CLK_PRED),
CLK_DIV("audio_podf", "audio_pred", CDCDR, SPDIF1_CLK_PODF),
CLK_DIV("vid_podf", "vid_sel", CSCMR2, VID_CLK_PODF),
CLK_DIV("can_podf", "can_sel", CSCMR2, CAN_CLK_PODF),
CLK_DIV("display_podf", "display_sel", CSCDR3, IPU2_HSP_PODF),
CLK_DIV("csi_podf", "csi_sel", CSCDR3, IPU1_HSP_PODF),
CLK_DIV("enet_podf", "enet_pre_sel", CHSCCDR, IPU1_DI1_PODF),
CLK_DIV("m4_podf", "m4_sel", CHSCCDR, IPU1_DI0_PODF),
CLK_DIV("ecspi_podf", "ecspi_sel", CSCDR2, ECSPI_CLK_PODF),
CLK_DIV("lcdif1_pred", "lcdif1_pre_sel", CSCDR2, IPU2_DI1_PODF),
CLK_DIV("lcdif2_pred", "lcdif2_pre_sel", CSCDR2, IPU2_DI0_PODF),
CLK_DIV("ssi1_pred", "ssi1_sel", CS1CDR, SSI1_CLK_PRED),
CLK_DIV("ssi1_podf", "ssi1_pred", CS1CDR, SSI1_CLK_PODF),
CLK_DIV("ssi2_pred", "ssi2_sel", CS2CDR, SSI2_CLK_PRED),
CLK_DIV("ssi2_podf", "ssi2_pred", CS2CDR, SSI2_CLK_PODF),
CLK_DIV("ssi3_pred", "ssi3_sel", CS1CDR, SSI3_CLK_PRED),
CLK_DIV("ssi3_podf", "ssi3_pred", CS1CDR, SSI3_CLK_PODF),
CLK_DIV("usdhc1_podf", "usdhc1_sel", CSCDR1, USDHC1_PODF),
CLK_DIV("usdhc2_podf", "usdhc2_sel", CSCDR1, USDHC2_PODF),
CLK_DIV("usdhc3_podf", "usdhc3_sel", CSCDR1, USDHC3_PODF),
CLK_DIV("usdhc4_podf", "usdhc4_sel", CSCDR1, USDHC4_PODF),
CLK_DIV("uart_podf", "uart_sel", CSCDR1, UART_CLK_PODF),
CLK_DIV("qspi2_pred", "qspi2_sel", CS2CDR, ENFC_CLK_PRED),
CLK_DIV("qspi2_podf", "qspi2_pred", CS2CDR, ENFC_CLK_PODF),
CLK_DIV("cko1_podf", "cko1_sel", CCOSR, CLKO1_DIV),
CLK_DIV("cko2_podf", "cko2_sel", CCOSR, CLKO2_DIV),
CLK_DIV("qspi1_podf", "qspi1_sel", CSCMR1, QSPI1_PODF),
CLK_DIV("eim_slow_podf", "eim_slow_sel", CSCMR1, ACLK_EIM_SLOW_PODF),
CLK_DIV("lcdif2_podf", "lcdif2_pred", CSCMR1, ACLK_PODF),
CLK_DIV("perclk", "perclk_sel", CSCMR1, PERCLK_PODF),
CLK_DIV("div_arm", "mout_cpu", EXYNOS5410_DIV_CPU0, __BITS(2,0)),
CLK_DIV("div_arm2", "div_arm", EXYNOS5410_DIV_CPU0, __BITS(30,28)),
CLK_DIV("div_acp", "div_arm2", EXYNOS5410_DIV_CPU0, __BITS(10,8)),
CLK_DIV("div_cpud", "div_arm2", EXYNOS5410_DIV_CPU0, __BITS(6,4)),
CLK_DIV("div_atb", "div_arm2", EXYNOS5410_DIV_CPU0, __BITS(18,16)),
CLK_DIV("pclk_dbg", "div_arm2", EXYNOS5410_DIV_CPU0, __BITS(22,20)),
CLK_DIV("div_kfc", "mout_kfc", EXYNOS5410_DIV_KFC0, __BITS(2,0)),
CLK_DIV("div_aclk", "div_kfc", EXYNOS5410_DIV_KFC0, __BITS(6,4)),
CLK_DIV("div_pclk", "div_kfc", EXYNOS5410_DIV_KFC0, __BITS(22,20)),
CLK_DIV("aclk66_pre", "sclk_mpll_muxed", EXYNOS5410_DIV_TOP1, __BITS(26,24)),
CLK_DIV("aclk66", "aclk66_pre", EXYNOS5410_DIV_TOP0, __BITS(2,0)),
CLK_DIV("dout_usbphy300", "mout_usbd300", EXYNOS5410_DIV_FSYS0, __BITS(19,16)),
CLK_DIV("dout_usbphy301", "mout_usbd301", EXYNOS5410_DIV_FSYS0, __BITS(23,20)),
CLK_DIV("dout_usbd300", "mout_usbd300", EXYNOS5410_DIV_FSYS0, __BITS(27,24)),
CLK_DIV("dout_usbd301", "mout_usbd301", EXYNOS5410_DIV_FSYS0, __BITS(31,28)),
CLK_DIV("dout_mmc0", "mout_mmc0", EXYNOS5410_DIV_FSYS1, __BITS(3,0)),
CLK_DIV("dout_mmc1", "mout_mmc1", EXYNOS5410_DIV_FSYS1, __BITS(19,16)),
CLK_DIV("dout_mmc2", "mout_mmc2", EXYNOS5410_DIV_FSYS2, __BITS(3,0)),
CLK_DIV("div_uart0", "mout_uart0", EXYNOS5410_DIV_PERIC0, __BITS(3,0)),
CLK_DIV("div_uart1", "mout_uart1", EXYNOS5410_DIV_PERIC0, __BITS(7,4)),
CLK_DIV("div_uart2", "mout_uart2", EXYNOS5410_DIV_PERIC0, __BITS(11,8)),
CLK_DIV("div_uart3", "mout_uart3", EXYNOS5410_DIV_PERIC0, __BITS(15,12)),
CLK_DIV("dout_pwm", "mout_pwm", EXYNOS5410_DIV_PERIC3, __BITS(3,0)),
CLK_DIV("aclk200", "mout_aclk200", EXYNOS5410_DIV_TOP0, __BITS(14,12)),
CLK_DIV("aclk266", "sclk_mpll_muxed", EXYNOS5410_DIV_TOP0, __BITS(18,16)),
CLK_DIV("aclk400", "mout_aclk400", EXYNOS5410_DIV_TOP0, __BITS(26,24)),
CLK_DIV("dout_aclk66", "mout_aclk66", EXYNOS5422_DIV_TOP1, __BITS(13,8)),
CLK_DIV("dout_aclk200_fsys", "mout_aclk200_fsys", EXYNOS5422_DIV_TOP0, __BITS(30,28)),
CLK_DIV("dout_aclk200_fsys2", "mout_aclk200_fsys2", EXYNOS5422_DIV_TOP0, __BITS(14,12)),
CLK_DIV("dout_usbphy301", "mout_usbd301", EXYNOS5422_DIV_FSYS0, __BITS(15,12)),
CLK_DIV("dout_usbphy300", "mout_usbd300", EXYNOS5422_DIV_FSYS0, __BITS(19,16)),
CLK_DIV("dout_usbd301", "mout_usbd301", EXYNOS5422_DIV_FSYS0, __BITS(23,20)),
CLK_DIV("dout_usbd300", "mout_usbd300", EXYNOS5422_DIV_FSYS0, __BITS(27,24)),
CLK_DIV("dout_mmc0", "mout_mmc0", EXYNOS5422_DIV_FSYS1, __BITS(9,0)),
CLK_DIV("dout_mmc1", "mout_mmc1", EXYNOS5422_DIV_FSYS1, __BITS(19,10)),
CLK_DIV("dout_mmc2", "mout_mmc2", EXYNOS5422_DIV_FSYS1, __BITS(29,20)),
CLK_DIV("dout_uart0", "mout_uart0", EXYNOS5422_DIV_PERIC0,
CLK_DIV("dout_uart1", "mout_uart1", EXYNOS5422_DIV_PERIC0,
CLK_DIV("dout_uart2", "mout_uart2", EXYNOS5422_DIV_PERIC0,
CLK_DIV("dout_uart3", "mout_uart3", EXYNOS5422_DIV_PERIC0,