sys/arch/sgimips/dev/scn.c

1399

sr = (SC)->sc_chbase[CH_SR]; \

sys/arch/sgimips/dev/scn.c

1414

sr = sc->sc_chbase[CH_SR];

sys/arch/sgimips/dev/scn.c

1420

sr = sc->sc_chbase[CH_SR];

sys/arch/sgimips/dev/scn.c

1827

while (sc->sc_chbase[CH_SR] & SR_TX_RDY) {

sys/arch/sgimips/dev/scn.c

1920

while ((ch_base[CH_SR] & SR_RX_RDY) == 0)

sys/arch/sgimips/dev/scn.c

1950

while ((ch_base[CH_SR] & SR_TX_RDY) == 0)

sys/arch/sgimips/dev/scn.c

1953

while ((ch_base[CH_SR] & SR_TX_RDY) == 0)

sys/arch/vax/boot/boot/consio.c

284

while ((vxtregs[CH_SR] & SR_TX_RDY) == 0)

sys/arch/vax/boot/boot/consio.c

292

while ((vxtregs[CH_SR] & SR_RX_RDY) == 0)

sys/arch/vax/boot/boot/consio.c

300

if ((vxtregs[CH_SR] & SR_RX_RDY) == 0)

sys/arch/vax/uba/qvaux.c

287

sc->sc_qr.qr_ch_regs[0].qr_sr = CH_SR(0);

sys/arch/vax/uba/qvaux.c

292

sc->sc_qr.qr_ch_regs[1].qr_sr = CH_SR(1);