sys/arch/sgimips/dev/scn.c

1035

ch_base[CH_CR] = CR_ENA_RX | CR_ENA_TX;

sys/arch/sgimips/dev/scn.c

1425

sc->sc_chbase[CH_CR] = CR_CMD_RESET_ERR; /* resets break? */

sys/arch/sgimips/dev/scn.c

1620

sc->sc_chbase[CH_CR] = CR_CMD_START_BRK;

sys/arch/sgimips/dev/scn.c

1624

sc->sc_chbase[CH_CR] = CR_CMD_STOP_BRK;

sys/arch/sgimips/dev/scn.c

437

dp->base[CH_CR] = CR_CMD_MR0;

sys/arch/sgimips/dev/scn.c

442

dp->base[CH_CR] = CR_CMD_MR0;

sys/arch/sgimips/dev/scn.c

450

sc->sc_chbase[CH_CR] = CR_CMD_MR0;

sys/arch/sgimips/dev/scn.c

455

sc->sc_chbase[CH_CR] = CR_CMD_MR0;

sys/arch/sgimips/dev/scn.c

461

sc->sc_chbase[CH_CR] = CR_CMD_MR1;

sys/arch/sgimips/dev/scn.c

469

sc->sc_chbase[CH_CR] = CR_CMD_MR1;

sys/arch/sgimips/dev/scn.c

847

ch_base[CH_CR] = CR_DIS_TX;

sys/arch/sgimips/dev/scn.c

850

ch_base[CH_CR] = CR_CMD_MR1;

sys/arch/sgimips/dev/scn.c

854

ch_base[CH_CR] = CR_CMD_MR1;

sys/arch/sgimips/dev/scn.c

858

ch_base[CH_CR] = CR_CMD_MR1;

sys/arch/sgimips/dev/scn.c

862

ch_base[CH_CR] = CR_CMD_MR0;

sys/arch/sgimips/dev/scn.c

866

ch_base[CH_CR] = CR_CMD_MR1;

sys/arch/sgimips/dev/scn.c

870

ch_base[CH_CR] = CR_CMD_MR0;

sys/arch/sgimips/dev/scn.c

878

ch_base[CH_CR] = CR_CMD_RTS_OFF;

sys/arch/sgimips/dev/scn.c

882

ch_base[CH_CR] = CR_CMD_RTS_OFF;

sys/arch/sgimips/dev/scn.c

896

ch_base[CH_CR] = CR_ENA_TX;

sys/arch/sgimips/dev/scn.c

899

ch_base[CH_CR] = CR_CMD_MR1;

sys/arch/sgimips/dev/scn.c

965

ch_base[CH_CR] = CR_DIS_RX | CR_DIS_TX;

sys/arch/sgimips/dev/scn.c

967

ch_base[CH_CR] = CR_CMD_RESET_RX;

sys/arch/sgimips/dev/scn.c

969

ch_base[CH_CR] = CR_CMD_RESET_TX;

sys/arch/sgimips/dev/scn.c

971

ch_base[CH_CR] = CR_CMD_RESET_ERR;

sys/arch/sgimips/dev/scn.c

973

ch_base[CH_CR] = CR_CMD_RESET_BRK;

sys/arch/sgimips/dev/scn.c

975

ch_base[CH_CR] = CR_CMD_MR1;

sys/arch/vax/uba/qvaux.c

289

sc->sc_qr.qr_ch_regs[0].qr_cr = CH_CR(0);

sys/arch/vax/uba/qvaux.c

294

sc->sc_qr.qr_ch_regs[1].qr_cr = CH_CR(1);