sys/arch/macppc/macppc/pic_ohare.c

147

ohare->enable_mask = 0;

sys/arch/macppc/macppc/pic_ohare.c

170

ohare->enable_mask |= mask;

sys/arch/macppc/macppc/pic_ohare.c

171

out32rb(INT_ENABLE_REG, ohare->enable_mask);

sys/arch/macppc/macppc/pic_ohare.c

181

ohare->enable_mask |= mask;

sys/arch/macppc/macppc/pic_ohare.c

182

out32rb(INT_ENABLE_REG, ohare->enable_mask);

sys/arch/macppc/macppc/pic_ohare.c

196

ohare->enable_mask &= ~mask;

sys/arch/macppc/macppc/pic_ohare.c

197

out32rb(INT_ENABLE_REG, ohare->enable_mask);

sys/arch/macppc/macppc/pic_ohare.c

209

levels = in32rb(INT_LEVEL_REG) & ohare->enable_mask;

sys/arch/macppc/macppc/pic_ohare.c

57

uint32_t enable_mask;

sys/arch/powerpc/marvell/pic_discovery.c

108

discovery->enable_mask = 0;

sys/arch/powerpc/marvell/pic_discovery.c

118

discovery->enable_mask |= (1 << irq);

sys/arch/powerpc/marvell/pic_discovery.c

127

discovery->enable_mask &= ~(1 << irq);

sys/arch/powerpc/pic/i8259_common.c

73

i8259->enable_mask = ~i8259->irqs;

sys/arch/powerpc/pic/i8259_common.c

74

isa_outb(IO_ICU1+1, i8259->enable_mask);

sys/arch/powerpc/pic/i8259_common.c

75

isa_outb(IO_ICU2+1, i8259->enable_mask >> 8);

sys/arch/powerpc/pic/i8259_common.c

84

i8259->enable_mask |= mask;

sys/arch/powerpc/pic/i8259_common.c

85

isa_outb(IO_ICU1+1, i8259->enable_mask);

sys/arch/powerpc/pic/i8259_common.c

86

isa_outb(IO_ICU2+1, i8259->enable_mask >> 8);

sys/arch/powerpc/pic/pic_i8259.c

72

i8259->enable_mask = 0xffffffff;

sys/arch/powerpc/pic/pic_prepivr.c

91

prepivr->enable_mask = 0xffffffff;

sys/arch/powerpc/pic/picvar.h

86

uint32_t enable_mask;

sys/dev/i2c/as3722.c

136

u_int enable_mask;

sys/dev/i2c/as3722.c

149

.enable_mask = AS3722_SDCONTROL_SD4_ENABLE,

sys/dev/i2c/as3722.c

156

.enable_mask = 0x40,

sys/dev/i2c/as3722.c

581

if (!regdef->enable_mask)

sys/dev/i2c/as3722.c

587

regdef->enable_mask, 0, flags);

sys/dev/i2c/as3722.c

590

0, regdef->enable_mask, flags);

sys/dev/i2c/rkpmic.c

102

.enable_reg = 0x23, .enable_mask = __BIT(0),

sys/dev/i2c/rkpmic.c

106

.enable_reg = 0x23, .enable_mask = __BIT(1),

sys/dev/i2c/rkpmic.c

110

.enable_reg = 0x23, .enable_mask = __BIT(2) },

sys/dev/i2c/rkpmic.c

112

.enable_reg = 0x23, .enable_mask = __BIT(3),

sys/dev/i2c/rkpmic.c

118

.enable_reg = 0x27, .enable_mask = __BIT(0),

sys/dev/i2c/rkpmic.c

122

.enable_reg = 0x27, .enable_mask = __BIT(1),

sys/dev/i2c/rkpmic.c

126

.enable_reg = 0x27, .enable_mask = __BIT(2),

sys/dev/i2c/rkpmic.c

140

.enable_reg = 0x23, .enable_mask = __BIT(0),

sys/dev/i2c/rkpmic.c

144

.enable_reg = 0x23, .enable_mask = __BIT(1),

sys/dev/i2c/rkpmic.c

148

.enable_reg = 0x23, .enable_mask = __BIT(2) },

sys/dev/i2c/rkpmic.c

150

.enable_reg = 0x23, .enable_mask = __BIT(3),

sys/dev/i2c/rkpmic.c

156

.enable_reg = 0x24, .enable_mask = __BIT(0),

sys/dev/i2c/rkpmic.c

160

.enable_reg = 0x24, .enable_mask = __BIT(1),

sys/dev/i2c/rkpmic.c

164

.enable_reg = 0x24, .enable_mask = __BIT(2),

sys/dev/i2c/rkpmic.c

168

.enable_reg = 0x24, .enable_mask = __BIT(3),

sys/dev/i2c/rkpmic.c

172

.enable_reg = 0x24, .enable_mask = __BIT(4),

sys/dev/i2c/rkpmic.c

176

.enable_reg = 0x24, .enable_mask = __BIT(5),

sys/dev/i2c/rkpmic.c

180

.enable_reg = 0x24, .enable_mask = __BIT(6),

sys/dev/i2c/rkpmic.c

184

.enable_reg = 0x24, .enable_mask = __BIT(7),

sys/dev/i2c/rkpmic.c

190

.enable_reg = 0x23, .enable_mask = __BIT(5) },

sys/dev/i2c/rkpmic.c

192

.enable_reg = 0x23, .enable_mask = __BIT(6) },

sys/dev/i2c/rkpmic.c

551

if (!c->enable_mask)

sys/dev/i2c/rkpmic.c

556

val |= c->enable_mask << 4;

sys/dev/i2c/rkpmic.c

560

val |= c->enable_mask;

sys/dev/i2c/rkpmic.c

562

val &= ~c->enable_mask;

sys/dev/i2c/rkpmic.c

81

uint8_t enable_mask;