emuxki_write
emuxki_write(sc, 0, EMU_ADCCR, 0);
emuxki_write(sc, 0, EMU_ADCBA, 0);
emuxki_write(sc, 0, EMU_ADCBS, 0);
emuxki_write(sc, 0, EMU_ADCCR,
emuxki_write(sc, 0, X1(ADCIDX), 0);
emuxki_write(sc, 0, EMU_ADCBA, DMAADDR(sc->rmem));
emuxki_write(sc, 0, EMU_ADCBS, EMU_REC_BUFSIZE_RECBS);
emuxki_write(sc, 0, EMU_CLIEL, 0);
emuxki_write(sc, 0, EMU_CLIEH, 0);
emuxki_write(sc, 0, EMU_SOLEL, 0);
emuxki_write(sc, 0, EMU_SOLEH, 0);
emuxki_write(sc, 0, X1(DBG), X1(DBG_SINGLE_STEP));
emuxki_write(sc, 0, EMU_CLIEL, 0);
emuxki_write(sc, 0, EMU_CLIEH, 0);
emuxki_write(sc, 0, EMU_SOLEL, 0);
emuxki_write(sc, 0, EMU_SOLEH, 0);
emuxki_write(sc, 0, EMU_MICBS, EMU_RECBS_BUFSIZE_NONE);
emuxki_write(sc, 0, EMU_MICBA, 0);
emuxki_write(sc, 0, EMU_FXBS, EMU_RECBS_BUFSIZE_NONE);
emuxki_write(sc, 0, EMU_FXBA, 0);
emuxki_write(sc, 0, EMU_ADCBS, EMU_RECBS_BUFSIZE_NONE);
emuxki_write(sc, 0, EMU_ADCBA, 0);
emuxki_write(sc, 0, EMU_SPBYPASS, EMU_SPBYPASS_24_BITS);
emuxki_write(sc, 0, EMU_AC97SLOT,
emuxki_write(sc, i, EMU_CHAN_DCYSUSV, 0x7f7f);
emuxki_write(sc, i, EMU_CHAN_IP, EMU_CHAN_IP_UNITY);
emuxki_write(sc, i, EMU_CHAN_VTFT, 0xffff);
emuxki_write(sc, i, EMU_CHAN_CVCF, 0xffff);
emuxki_write(sc, i, EMU_CHAN_PTRX, 0);
emuxki_write(sc, i, EMU_CHAN_CPF, 0);
emuxki_write(sc, i, EMU_CHAN_CCR, 0);
emuxki_write(sc, i, EMU_CHAN_PSST, 0);
emuxki_write(sc, i, EMU_CHAN_DSL, 0);
emuxki_write(sc, i, EMU_CHAN_CCCA, EMU_CHAN_CCCA_INTERPROM_1);
emuxki_write(sc, i, EMU_CHAN_Z1, 0);
emuxki_write(sc, i, EMU_CHAN_Z2, 0);
emuxki_write(sc, i, EMU_CHAN_MAPA, 0xffffffff);
emuxki_write(sc, i, EMU_CHAN_MAPB, 0xffffffff);
emuxki_write(sc, i, EMU_CHAN_FXRT, 0x32100000);
emuxki_write(sc, i, EMU_CHAN_ATKHLDM, 0);
emuxki_write(sc, i, EMU_CHAN_DCYSUSM, 0);
emuxki_write(sc, i, EMU_CHAN_IFATN, 0xffff);
emuxki_write(sc, i, EMU_CHAN_PEFE, 0x007f);
emuxki_write(sc, i, EMU_CHAN_FMMOD, 0);
emuxki_write(sc, i, EMU_CHAN_TREMFRQ, 0);
emuxki_write(sc, i, EMU_CHAN_FM2FRQ2, 0);
emuxki_write(sc, i, EMU_CHAN_TEMPENV, 0);
emuxki_write(sc, i, EMU_CHAN_LFOVAL2, 0x8000);
emuxki_write(sc, i, EMU_CHAN_LFOVAL1, 0x8000);
emuxki_write(sc, i, EMU_CHAN_ATKHLDV, 0x7f7f);
emuxki_write(sc, i, EMU_CHAN_ENVVOL, 0);
emuxki_write(sc, i, EMU_CHAN_ENVVAL, 0x8000);
emuxki_write(sc, 0, EMU_SPCS0, spcs);
emuxki_write(sc, 0, EMU_SPCS1, spcs);
emuxki_write(sc, 0, EMU_SPCS2, spcs);
emuxki_write(sc, 0, EMU_A2_SPDIF_SAMPLERATE,
emuxki_write(sc, 0, EMU_A2_SPDIF_SAMPLERATE,
emuxki_write(sc, 0, EMU_PTB, DMAADDR(sc->ptb));
emuxki_write(sc, 0, EMU_TCBS, 0); /* This means 16K TCB */
emuxki_write(sc, 0, EMU_TCB, 0); /* No TCB use for now */
emuxki_write(sc, 0, reg, loword);
emuxki_write(sc, 0, reg + 1, hiword);
emuxki_write(sc, 0, EMU_DSP_GPR(pc), 0);
emuxki_write(sc, 0, EMU_TANKMEMDATAREGBASE + pc, 0);
emuxki_write(sc, 0, EMU_TANKMEMADDRREGBASE + pc, 0);
emuxki_write(sc, 0, X1(DBG), X1(DBG_SINGLE_STEP));
emuxki_write(sc, 0, X1(DBG), 0);
emuxki_write(sc, ch, EMU_CHAN_DSL,
emuxki_write(sc, ch, EMU_CHAN_PSST,
emuxki_write(sc, ch, EMU_CHAN_VTFT,
emuxki_write(sc, ch, EMU_CHAN_CVCF,
emuxki_write(sc, ch, EMU_CHAN_PTRX,
emuxki_write(sc, ch, EMU_CHAN_CPF,
emuxki_write(sc, ch, EMU_CHAN_CPF, EMU_CHAN_CPF_STOP_MASK);
emuxki_write(sc, ch, EMU_CHAN_CVCF, 0);
emuxki_write(sc, 0, EMU_ADCCR, 0);
static void emuxki_write(struct emuxki_softc *, int, int, uint32_t);