cr3
x86_gva_to_gpa_32bit(struct nvmm_machine *mach, uint64_t cr3,
L2gpa = (cr3 & CR3_FRAME_32BIT);
x86_gva_to_gpa_32bit_pae(struct nvmm_machine *mach, uint64_t cr3,
L3gpa = (cr3 & CR3_FRAME_32BIT_PAE);
x86_gva_to_gpa_64bit(struct nvmm_machine *mach, uint64_t cr3,
L4gpa = (cr3 & CR3_FRAME_64BIT);
uint64_t cr3;
cr3 = state->crs[NVMM_X64_CR_CR3];
ret = x86_gva_to_gpa_64bit(mach, cr3, gva, gpa, prot);
ret = x86_gva_to_gpa_32bit_pae(mach, cr3, gva, gpa, prot);
ret = x86_gva_to_gpa_32bit(mach, cr3, gva, gpa, has_pse, prot);
uint64_t cr3;
store->cr3 = pmap_pdirpa(pmap_kernel(), 0);
sc->sc_active.cr3 =
cmd[1] = sc->sc_active.cr3;
sc->sc_shadow.cr3 =
(sc->sc_shadow.cr3 & ~CR3_OPMODE_MASK) |
sc->sc_shadow.cr3 =
(sc->sc_shadow.cr3 & ~CR3_OPMODE_MASK) |
sc->sc_shadow.cr3, sc->sc_shadow.cr4, sc->sc_shadow.output_mute);
if (sc->sc_active.cr3 != sc->sc_shadow.cr3) {
cmd[0] = sc->sc_shadow.cr3;
sc->sc_active.cr3 = sc->sc_shadow.cr3;
if ((sc->sc_active.cr3 & CR3_OPMODE_MASK) != CR3_OPMODE_NORMAL)
arcofi_cr3_to_portmask(uint cr3, int output_mute)
switch (cr3 & CR3_AFEC_MASK) {
if ((cr3 & CR3_MIC_G_MASK) == CR3_MIC_X_INPUT)
portmask = arcofi_cr3_to_portmask(sc->sc_shadow.cr3,
sc->sc_shadow.cr3, portmask);
sc->sc_shadow.cr3 = (sc->sc_shadow.cr3 & CR3_OPMODE_MASK) |
portmask, sc->sc_shadow.cr3, sc->sc_shadow.output_mute);
portmask = arcofi_cr3_to_portmask(sc->sc_shadow.cr3,
sc->sc_shadow.cr3, portmask);
uint8_t cr3, cr4;
if (vmcb->state.cr3 != state->crs[NVMM_X64_CR_CR3]) {
vmcb->state.cr3 = state->crs[NVMM_X64_CR_CR3];
state->crs[NVMM_X64_CR_CR3] = vmcb->state.cr3;
uint64_t cr3;
uint64_t cr0, cr3, cr4, efer;
cr3 = vmx_vmread(VMCS_GUEST_CR3);
if (cr3 != state->crs[NVMM_X64_CR_CR3]) {