cpu_reg - NetBSD

sys/dev/pci/if_bnx.c

2845

bnx_load_cpu_fw(struct bnx_softc *sc, struct cpu_reg *cpu_reg,

sys/dev/pci/if_bnx.c

2852

val = REG_RD_IND(sc, cpu_reg->mode);

sys/dev/pci/if_bnx.c

2853

val |= cpu_reg->mode_value_halt;

sys/dev/pci/if_bnx.c

2854

REG_WR_IND(sc, cpu_reg->mode, val);

sys/dev/pci/if_bnx.c

2855

REG_WR_IND(sc, cpu_reg->state, cpu_reg->state_value_clear);

sys/dev/pci/if_bnx.c

2858

offset = cpu_reg->spad_base + (fw->text_addr - cpu_reg->mips_view_base);

sys/dev/pci/if_bnx.c

2867

offset = cpu_reg->spad_base + (fw->data_addr - cpu_reg->mips_view_base);

sys/dev/pci/if_bnx.c

2876

offset = cpu_reg->spad_base + (fw->sbss_addr - cpu_reg->mips_view_base);

sys/dev/pci/if_bnx.c

2885

offset = cpu_reg->spad_base + (fw->bss_addr - cpu_reg->mips_view_base);

sys/dev/pci/if_bnx.c

2894

offset = cpu_reg->spad_base +

sys/dev/pci/if_bnx.c

2895

(fw->rodata_addr - cpu_reg->mips_view_base);

sys/dev/pci/if_bnx.c

2904

REG_WR_IND(sc, cpu_reg->inst, 0);

sys/dev/pci/if_bnx.c

2905

REG_WR_IND(sc, cpu_reg->pc, fw->start_addr);

sys/dev/pci/if_bnx.c

2908

val = REG_RD_IND(sc, cpu_reg->mode);

sys/dev/pci/if_bnx.c

2909

val &= ~cpu_reg->mode_value_halt;

sys/dev/pci/if_bnx.c

2910

REG_WR_IND(sc, cpu_reg->state, cpu_reg->state_value_clear);

sys/dev/pci/if_bnx.c

2911

REG_WR_IND(sc, cpu_reg->mode, val);

sys/dev/pci/if_bnx.c

2925

struct cpu_reg cpu_reg;

sys/dev/pci/if_bnx.c

2944

cpu_reg.mode = BNX_RXP_CPU_MODE;

sys/dev/pci/if_bnx.c

2945

cpu_reg.mode_value_halt = BNX_RXP_CPU_MODE_SOFT_HALT;

sys/dev/pci/if_bnx.c

2946

cpu_reg.mode_value_sstep = BNX_RXP_CPU_MODE_STEP_ENA;

sys/dev/pci/if_bnx.c

2947

cpu_reg.state = BNX_RXP_CPU_STATE;

sys/dev/pci/if_bnx.c

2948

cpu_reg.state_value_clear = 0xffffff;

sys/dev/pci/if_bnx.c

2949

cpu_reg.gpr0 = BNX_RXP_CPU_REG_FILE;

sys/dev/pci/if_bnx.c

2950

cpu_reg.evmask = BNX_RXP_CPU_EVENT_MASK;

sys/dev/pci/if_bnx.c

2951

cpu_reg.pc = BNX_RXP_CPU_PROGRAM_COUNTER;

sys/dev/pci/if_bnx.c

2952

cpu_reg.inst = BNX_RXP_CPU_INSTRUCTION;

sys/dev/pci/if_bnx.c

2953

cpu_reg.bp = BNX_RXP_CPU_HW_BREAKPOINT;

sys/dev/pci/if_bnx.c

2954

cpu_reg.spad_base = BNX_RXP_SCRATCH;

sys/dev/pci/if_bnx.c

2955

cpu_reg.mips_view_base = 0x8000000;

sys/dev/pci/if_bnx.c

2988

bnx_load_cpu_fw(sc, &cpu_reg, &fw);

sys/dev/pci/if_bnx.c

2991

cpu_reg.mode = BNX_TXP_CPU_MODE;

sys/dev/pci/if_bnx.c

2992

cpu_reg.mode_value_halt = BNX_TXP_CPU_MODE_SOFT_HALT;

sys/dev/pci/if_bnx.c

2993

cpu_reg.mode_value_sstep = BNX_TXP_CPU_MODE_STEP_ENA;

sys/dev/pci/if_bnx.c

2994

cpu_reg.state = BNX_TXP_CPU_STATE;

sys/dev/pci/if_bnx.c

2995

cpu_reg.state_value_clear = 0xffffff;

sys/dev/pci/if_bnx.c

2996

cpu_reg.gpr0 = BNX_TXP_CPU_REG_FILE;

sys/dev/pci/if_bnx.c

2997

cpu_reg.evmask = BNX_TXP_CPU_EVENT_MASK;

sys/dev/pci/if_bnx.c

2998

cpu_reg.pc = BNX_TXP_CPU_PROGRAM_COUNTER;

sys/dev/pci/if_bnx.c

2999

cpu_reg.inst = BNX_TXP_CPU_INSTRUCTION;

sys/dev/pci/if_bnx.c

3000

cpu_reg.bp = BNX_TXP_CPU_HW_BREAKPOINT;

sys/dev/pci/if_bnx.c

3001

cpu_reg.spad_base = BNX_TXP_SCRATCH;

sys/dev/pci/if_bnx.c

3002

cpu_reg.mips_view_base = 0x8000000;

sys/dev/pci/if_bnx.c

3035

bnx_load_cpu_fw(sc, &cpu_reg, &fw);

sys/dev/pci/if_bnx.c

3038

cpu_reg.mode = BNX_TPAT_CPU_MODE;

sys/dev/pci/if_bnx.c

3039

cpu_reg.mode_value_halt = BNX_TPAT_CPU_MODE_SOFT_HALT;

sys/dev/pci/if_bnx.c

3040

cpu_reg.mode_value_sstep = BNX_TPAT_CPU_MODE_STEP_ENA;

sys/dev/pci/if_bnx.c

3041

cpu_reg.state = BNX_TPAT_CPU_STATE;

sys/dev/pci/if_bnx.c

3042

cpu_reg.state_value_clear = 0xffffff;

sys/dev/pci/if_bnx.c

3043

cpu_reg.gpr0 = BNX_TPAT_CPU_REG_FILE;

sys/dev/pci/if_bnx.c

3044

cpu_reg.evmask = BNX_TPAT_CPU_EVENT_MASK;

sys/dev/pci/if_bnx.c

3045

cpu_reg.pc = BNX_TPAT_CPU_PROGRAM_COUNTER;

sys/dev/pci/if_bnx.c

3046

cpu_reg.inst = BNX_TPAT_CPU_INSTRUCTION;

sys/dev/pci/if_bnx.c

3047

cpu_reg.bp = BNX_TPAT_CPU_HW_BREAKPOINT;

sys/dev/pci/if_bnx.c

3048

cpu_reg.spad_base = BNX_TPAT_SCRATCH;

sys/dev/pci/if_bnx.c

3049

cpu_reg.mips_view_base = 0x8000000;

sys/dev/pci/if_bnx.c

3082

bnx_load_cpu_fw(sc, &cpu_reg, &fw);

sys/dev/pci/if_bnx.c

3085

cpu_reg.mode = BNX_COM_CPU_MODE;

sys/dev/pci/if_bnx.c

3086

cpu_reg.mode_value_halt = BNX_COM_CPU_MODE_SOFT_HALT;

sys/dev/pci/if_bnx.c

3087

cpu_reg.mode_value_sstep = BNX_COM_CPU_MODE_STEP_ENA;

sys/dev/pci/if_bnx.c

3088

cpu_reg.state = BNX_COM_CPU_STATE;

sys/dev/pci/if_bnx.c

3089

cpu_reg.state_value_clear = 0xffffff;

sys/dev/pci/if_bnx.c

3090

cpu_reg.gpr0 = BNX_COM_CPU_REG_FILE;

sys/dev/pci/if_bnx.c

3091

cpu_reg.evmask = BNX_COM_CPU_EVENT_MASK;

sys/dev/pci/if_bnx.c

3092

cpu_reg.pc = BNX_COM_CPU_PROGRAM_COUNTER;

sys/dev/pci/if_bnx.c

3093

cpu_reg.inst = BNX_COM_CPU_INSTRUCTION;

sys/dev/pci/if_bnx.c

3094

cpu_reg.bp = BNX_COM_CPU_HW_BREAKPOINT;

sys/dev/pci/if_bnx.c

3095

cpu_reg.spad_base = BNX_COM_SCRATCH;

sys/dev/pci/if_bnx.c

3096

cpu_reg.mips_view_base = 0x8000000;

sys/dev/pci/if_bnx.c

3128

bnx_load_cpu_fw(sc, &cpu_reg, &fw);

sys/dev/pci/if_bnx.c

3138

cpu_reg.mode = BNX_RXP_CPU_MODE;

sys/dev/pci/if_bnx.c

3139

cpu_reg.mode_value_halt = BNX_RXP_CPU_MODE_SOFT_HALT;

sys/dev/pci/if_bnx.c

3140

cpu_reg.mode_value_sstep = BNX_RXP_CPU_MODE_STEP_ENA;

sys/dev/pci/if_bnx.c

3141

cpu_reg.state = BNX_RXP_CPU_STATE;

sys/dev/pci/if_bnx.c

3142

cpu_reg.state_value_clear = 0xffffff;

sys/dev/pci/if_bnx.c

3143

cpu_reg.gpr0 = BNX_RXP_CPU_REG_FILE;

sys/dev/pci/if_bnx.c

3144

cpu_reg.evmask = BNX_RXP_CPU_EVENT_MASK;

sys/dev/pci/if_bnx.c

3145

cpu_reg.pc = BNX_RXP_CPU_PROGRAM_COUNTER;

sys/dev/pci/if_bnx.c

3146

cpu_reg.inst = BNX_RXP_CPU_INSTRUCTION;

sys/dev/pci/if_bnx.c

3147

cpu_reg.bp = BNX_RXP_CPU_HW_BREAKPOINT;

sys/dev/pci/if_bnx.c

3148

cpu_reg.spad_base = BNX_RXP_SCRATCH;

sys/dev/pci/if_bnx.c

3149

cpu_reg.mips_view_base = 0x8000000;

sys/dev/pci/if_bnx.c

3182

bnx_load_cpu_fw(sc, &cpu_reg, &fw);

sys/dev/pci/if_bnx.c

3185

cpu_reg.mode = BNX_TXP_CPU_MODE;

sys/dev/pci/if_bnx.c

3186

cpu_reg.mode_value_halt = BNX_TXP_CPU_MODE_SOFT_HALT;

sys/dev/pci/if_bnx.c

3187

cpu_reg.mode_value_sstep = BNX_TXP_CPU_MODE_STEP_ENA;

sys/dev/pci/if_bnx.c

3188

cpu_reg.state = BNX_TXP_CPU_STATE;

sys/dev/pci/if_bnx.c

3189

cpu_reg.state_value_clear = 0xffffff;

sys/dev/pci/if_bnx.c

3190

cpu_reg.gpr0 = BNX_TXP_CPU_REG_FILE;

sys/dev/pci/if_bnx.c

3191

cpu_reg.evmask = BNX_TXP_CPU_EVENT_MASK;

sys/dev/pci/if_bnx.c

3192

cpu_reg.pc = BNX_TXP_CPU_PROGRAM_COUNTER;

sys/dev/pci/if_bnx.c

3193

cpu_reg.inst = BNX_TXP_CPU_INSTRUCTION;

sys/dev/pci/if_bnx.c

3194

cpu_reg.bp = BNX_TXP_CPU_HW_BREAKPOINT;

sys/dev/pci/if_bnx.c

3195

cpu_reg.spad_base = BNX_TXP_SCRATCH;

sys/dev/pci/if_bnx.c

3196

cpu_reg.mips_view_base = 0x8000000;

sys/dev/pci/if_bnx.c

3229

bnx_load_cpu_fw(sc, &cpu_reg, &fw);

sys/dev/pci/if_bnx.c

3232

cpu_reg.mode = BNX_TPAT_CPU_MODE;

sys/dev/pci/if_bnx.c

3233

cpu_reg.mode_value_halt = BNX_TPAT_CPU_MODE_SOFT_HALT;

sys/dev/pci/if_bnx.c

3234

cpu_reg.mode_value_sstep = BNX_TPAT_CPU_MODE_STEP_ENA;

sys/dev/pci/if_bnx.c

3235

cpu_reg.state = BNX_TPAT_CPU_STATE;

sys/dev/pci/if_bnx.c

3236

cpu_reg.state_value_clear = 0xffffff;

sys/dev/pci/if_bnx.c

3237

cpu_reg.gpr0 = BNX_TPAT_CPU_REG_FILE;

sys/dev/pci/if_bnx.c

3238

cpu_reg.evmask = BNX_TPAT_CPU_EVENT_MASK;

sys/dev/pci/if_bnx.c

3239

cpu_reg.pc = BNX_TPAT_CPU_PROGRAM_COUNTER;

sys/dev/pci/if_bnx.c

3240

cpu_reg.inst = BNX_TPAT_CPU_INSTRUCTION;

sys/dev/pci/if_bnx.c

3241

cpu_reg.bp = BNX_TPAT_CPU_HW_BREAKPOINT;

sys/dev/pci/if_bnx.c

3242

cpu_reg.spad_base = BNX_TPAT_SCRATCH;

sys/dev/pci/if_bnx.c

3243

cpu_reg.mips_view_base = 0x8000000;

sys/dev/pci/if_bnx.c

3276

bnx_load_cpu_fw(sc, &cpu_reg, &fw);

sys/dev/pci/if_bnx.c

3279

cpu_reg.mode = BNX_COM_CPU_MODE;

sys/dev/pci/if_bnx.c

3280

cpu_reg.mode_value_halt = BNX_COM_CPU_MODE_SOFT_HALT;

sys/dev/pci/if_bnx.c

3281

cpu_reg.mode_value_sstep = BNX_COM_CPU_MODE_STEP_ENA;

sys/dev/pci/if_bnx.c

3282

cpu_reg.state = BNX_COM_CPU_STATE;

sys/dev/pci/if_bnx.c

3283

cpu_reg.state_value_clear = 0xffffff;

sys/dev/pci/if_bnx.c

3284

cpu_reg.gpr0 = BNX_COM_CPU_REG_FILE;

sys/dev/pci/if_bnx.c

3285

cpu_reg.evmask = BNX_COM_CPU_EVENT_MASK;

sys/dev/pci/if_bnx.c

3286

cpu_reg.pc = BNX_COM_CPU_PROGRAM_COUNTER;

sys/dev/pci/if_bnx.c

3287

cpu_reg.inst = BNX_COM_CPU_INSTRUCTION;

sys/dev/pci/if_bnx.c

3288

cpu_reg.bp = BNX_COM_CPU_HW_BREAKPOINT;

sys/dev/pci/if_bnx.c

3289

cpu_reg.spad_base = BNX_COM_SCRATCH;

sys/dev/pci/if_bnx.c

3290

cpu_reg.mips_view_base = 0x8000000;

sys/dev/pci/if_bnx.c

3322

bnx_load_cpu_fw(sc, &cpu_reg, &fw);

sys/dev/pci/if_bnx.c

360

void bnx_load_cpu_fw(struct bnx_softc *, struct cpu_reg *,