sys/dev/cadence/if_cemac.c

1007

cfg = CEMAC_READ(ETH_CFG);

sys/dev/cadence/if_cemac.c

1064

u = CEMAC_READ(ETH_TSR);

sys/dev/cadence/if_cemac.c

1068

u = CEMAC_READ(ETH_RSR);

sys/dev/cadence/if_cemac.c

1090

uint32_t ctl = CEMAC_READ(ETH_CTL);

sys/dev/cadence/if_cemac.c

1091

uint32_t cfg = CEMAC_READ(ETH_CFG);

sys/dev/cadence/if_cemac.c

180

u = CEMAC_READ(ETH_TSR);

sys/dev/cadence/if_cemac.c

184

u = CEMAC_READ(ETH_RSR);

sys/dev/cadence/if_cemac.c

203

tsr = CEMAC_READ(ETH_TSR);

sys/dev/cadence/if_cemac.c

262

imr = ~CEMAC_READ(ETH_IMR);

sys/dev/cadence/if_cemac.c

270

isr = CEMAC_READ(ETH_ISR);

sys/dev/cadence/if_cemac.c

280

rsr = CEMAC_READ(ETH_RSR); // get receive status register

sys/dev/cadence/if_cemac.c

291

ctl = CEMAC_READ(ETH_CTL);

sys/dev/cadence/if_cemac.c

385

irq = CEMAC_READ(IntStsC);

sys/dev/cadence/if_cemac.c

456

u = CEMAC_READ(ETH_TSR);

sys/dev/cadence/if_cemac.c

460

u = CEMAC_READ(ETH_RSR);

sys/dev/cadence/if_cemac.c

692

while (!(CEMAC_READ(ETH_SR) & ETH_SR_IDLE))

sys/dev/cadence/if_cemac.c

695

*val = CEMAC_READ(ETH_MAN) & ETH_MAN_DATA;

sys/dev/cadence/if_cemac.c

709

while (!(CEMAC_READ(ETH_SR) & ETH_SR_IDLE))

sys/dev/cadence/if_cemac.c

727

reg = CEMAC_READ(ETH_CFG);

sys/dev/cadence/if_cemac.c

796

CEMAC_READ(GEM_SCOL) + CEMAC_READ(GEM_MCOL));

sys/dev/cadence/if_cemac.c

799

CEMAC_READ(ETH_SCOL) + CEMAC_READ(ETH_MCOL));

sys/dev/cadence/if_cemac.c

803

uint32_t misses = CEMAC_READ(ETH_DRFC);

sys/dev/cadence/if_cemac.c

954

uint32_t ctl = CEMAC_READ(ETH_CTL) | GEM_CTL_STARTTX;

sys/dev/cadence/if_cemac.c

957

CEMAC_READ(ETH_CTL)));

sys/dev/cadence/if_cemac.c

978

CEMAC_READ(ETH_CTL), CEMAC_READ(ETH_CFG));

sys/dev/cadence/if_cemac.c

999

dma = CEMAC_READ(GEM_DMA_CFG);