cpsw_write_4
cpsw_write_4(sc, CPSW_CPDMA_RX_INTMASK_CLEAR, 0xFFFFFFFF);
cpsw_write_4(sc, CPSW_CPDMA_TX_INTMASK_CLEAR, 0xFFFFFFFF);
cpsw_write_4(sc, CPSW_CPDMA_TX_CONTROL, 1);
cpsw_write_4(sc, CPSW_CPDMA_RX_CONTROL, 1);
cpsw_write_4(sc, CPSW_WR_C_TX_EN(0), 1);
cpsw_write_4(sc, CPSW_WR_C_RX_EN(0), 1);
cpsw_write_4(sc, CPSW_WR_C_MISC_EN(0), 0x1F);
cpsw_write_4(sc, CPSW_CPDMA_DMA_INTMASK_SET, 2);
cpsw_write_4(sc, CPSW_CPDMA_TX_INTMASK_SET, 1);
cpsw_write_4(sc, CPSW_CPDMA_RX_INTMASK_SET, 1);
cpsw_write_4(sc, CPSW_CPDMA_CPDMA_EOI_VECTOR, CPSW_INTROFF_RXTH);
cpsw_write_4(sc, CPSW_CPDMA_CPDMA_EOI_VECTOR, CPSW_INTROFF_RX);
cpsw_write_4(sc, CPSW_CPDMA_CPDMA_EOI_VECTOR, CPSW_INTROFF_TX);
cpsw_write_4(sc, CPSW_CPDMA_CPDMA_EOI_VECTOR, CPSW_INTROFF_MISC);
cpsw_write_4(sc, MDIOCONTROL,
cpsw_write_4(sc, CPSW_CPDMA_RX_HDP(0), cpsw_rxdesc_paddr(sc, 0));
cpsw_write_4(sc, CPSW_CPDMA_TX_INTMASK_CLEAR, 1);
cpsw_write_4(sc, CPSW_CPDMA_RX_INTMASK_CLEAR, 1);
cpsw_write_4(sc, CPSW_WR_C_TX_EN(0), 0x0);
cpsw_write_4(sc, CPSW_WR_C_RX_EN(0), 0x0);
cpsw_write_4(sc, CPSW_WR_C_MISC_EN(0), 0x0);
cpsw_write_4(sc, CPSW_CPDMA_TX_TEARDOWN, 0);
cpsw_write_4(sc, CPSW_CPDMA_RX_TEARDOWN, 0);
cpsw_write_4(sc, CPSW_WR_SOFT_RESET, 1);
cpsw_write_4(sc, CPSW_SS_SOFT_RESET, 1);
cpsw_write_4(sc, CPSW_SL_SOFT_RESET(i), 1);
cpsw_write_4(sc, CPSW_CPDMA_SOFT_RESET, 1);
cpsw_write_4(sc, CPSW_CPDMA_CPDMA_EOI_VECTOR, CPSW_INTROFF_RXTH);
cpsw_write_4(sc, CPSW_CPDMA_RX_CP(0),
cpsw_write_4(sc, CPSW_CPDMA_CPDMA_EOI_VECTOR, CPSW_INTROFF_RX);
cpsw_write_4(sc, CPSW_CPDMA_TX_CP(0), 0xfffffffc);
cpsw_write_4(sc, CPSW_CPDMA_TX_HDP(0), 0);
cpsw_write_4(sc, CPSW_CPDMA_TX_CP(0),
cpsw_write_4(sc, CPSW_CPDMA_CPDMA_EOI_VECTOR, CPSW_INTROFF_TX);
cpsw_write_4(sc, CPSW_CPDMA_TX_HDP(0),
cpsw_write_4(sc, CPSW_CPDMA_DMA_INTMASK_CLEAR, dmastat);
cpsw_write_4(sc, CPSW_CPDMA_CPDMA_EOI_VECTOR, CPSW_INTROFF_MISC);
cpsw_write_4(sc, CPSW_PORT_P_SA_HI(port),
cpsw_write_4(sc, CPSW_PORT_P_SA_LO(port),
cpsw_write_4(sc, CPSW_ALE_TBLCTL, idx & 1023);
cpsw_write_4(sc, CPSW_ALE_TBLW0, ale_entry[0]);
cpsw_write_4(sc, CPSW_ALE_TBLW1, ale_entry[1]);
cpsw_write_4(sc, CPSW_ALE_TBLW2, ale_entry[2]);
cpsw_write_4(sc, CPSW_ALE_TBLCTL, 1 << 31 | (idx & 1023));
cpsw_write_4(sc, MDIOCONTROL,
cpsw_write_4(sc, CPSW_ALE_CONTROL, ALECTL_CLEAR_TABLE);
cpsw_write_4(sc, CPSW_CPDMA_TX_HDP(0),
cpsw_write_4(sc, MDIOUSERACCESS0, (1 << 31) |
cpsw_write_4(sc, MDIOUSERACCESS0, (1 << 31) | (1 << 30) |
cpsw_write_4(sc, CPSW_WR_SOFT_RESET, 1);
cpsw_write_4(sc, CPSW_SS_SOFT_RESET, 1);
cpsw_write_4(sc, CPSW_ALE_CONTROL,
cpsw_write_4(sc, CPSW_SL_SOFT_RESET(i), 1);
cpsw_write_4(sc, CPSW_SL_RX_PRI_MAP(i), 0x76543210);
cpsw_write_4(sc, CPSW_PORT_P_TX_PRI_MAP(i+1), 0x33221100);
cpsw_write_4(sc, CPSW_SL_RX_MAXLEN(i), 0x5f2);
cpsw_write_4(sc, CPSW_PORT_P_SA_HI(i+1),
cpsw_write_4(sc, CPSW_PORT_P_SA_LO(i+1),
cpsw_write_4(sc, CPSW_SL_MACCONTROL(i), macctl);
cpsw_write_4(sc, CPSW_ALE_PORTCTL(i+1), 3);
cpsw_write_4(sc, CPSW_PORT_P0_CPDMA_TX_PRI_MAP, 0x76543210);
cpsw_write_4(sc, CPSW_PORT_P0_CPDMA_RX_CH_MAP, 0);
cpsw_write_4(sc, CPSW_ALE_PORTCTL(0), 3);
cpsw_write_4(sc, CPSW_SS_PTYPE, 0);
cpsw_write_4(sc, CPSW_SS_STAT_PORT_EN, 7);
cpsw_write_4(sc, CPSW_CPDMA_SOFT_RESET, 1);
cpsw_write_4(sc, CPSW_CPDMA_TX_HDP(i), 0);
cpsw_write_4(sc, CPSW_CPDMA_RX_HDP(i), 0);
cpsw_write_4(sc, CPSW_CPDMA_TX_CP(i), 0);
cpsw_write_4(sc, CPSW_CPDMA_RX_CP(i), 0);
cpsw_write_4(sc, CPSW_CPDMA_RX_FREEBUFFER(0), 0);
cpsw_write_4(sc, CPSW_SS_FLOW_CONTROL, 0);
cpsw_write_4(sc, CPSW_CPDMA_RX_BUFFER_OFFSET, ETHER_ALIGN);