sys/arch/evbppc/virtex/design_gsrd1.c

286

chan->dmac_stat_addr = CDMAC_STAT_BASE(n);

sys/arch/evbppc/virtex/design_gsrd1.c

330

bus_space_write_4(&cdmac_bst, 0, CDMAC_STAT_BASE(0), CDMAC_STAT_RESET);

sys/arch/evbppc/virtex/design_gsrd1.c

331

bus_space_write_4(&cdmac_bst, 0, CDMAC_STAT_BASE(1), CDMAC_STAT_RESET);

sys/arch/evbppc/virtex/design_gsrd1.c

332

bus_space_write_4(&cdmac_bst, 0, CDMAC_STAT_BASE(2), CDMAC_STAT_RESET);

sys/arch/evbppc/virtex/design_gsrd1.c

333

bus_space_write_4(&cdmac_bst, 0, CDMAC_STAT_BASE(3), CDMAC_STAT_RESET);

sys/arch/evbppc/virtex/design_gsrd1.c

63

#define CDMAC_TX0_STAT CDMAC_STAT_BASE(0)

sys/arch/evbppc/virtex/design_gsrd1.c

64

#define CDMAC_RX0_STAT CDMAC_STAT_BASE(1)

sys/arch/evbppc/virtex/design_gsrd1.c

65

#define CDMAC_TX1_STAT CDMAC_STAT_BASE(2)

sys/arch/evbppc/virtex/design_gsrd1.c

66

#define CDMAC_RX1_STAT CDMAC_STAT_BASE(3)

sys/arch/evbppc/virtex/design_gsrd2.c

171

WCASE(DCR_CDMAC_BASE, CDMAC_STAT_BASE(0)); /* Tx engine */

sys/arch/evbppc/virtex/design_gsrd2.c

172

WCASE(DCR_CDMAC_BASE, CDMAC_STAT_BASE(1)); /* Rx engine */

sys/arch/evbppc/virtex/design_gsrd2.c

188

RCASE(DCR_CDMAC_BASE, CDMAC_STAT_BASE(0)); /* Tx engine */

sys/arch/evbppc/virtex/design_gsrd2.c

189

RCASE(DCR_CDMAC_BASE, CDMAC_STAT_BASE(1)); /* Rx engine */

sys/arch/evbppc/virtex/design_gsrd2.c

343

chan->dmac_stat_addr = CDMAC_STAT_BASE(idx);

sys/arch/evbppc/virtex/design_gsrd2.c

389

bus_space_write_4(&cdmac_bst, 0, CDMAC_STAT_BASE(0), CDMAC_STAT_RESET);

sys/arch/evbppc/virtex/design_gsrd2.c

390

bus_space_write_4(&cdmac_bst, 0, CDMAC_STAT_BASE(1), CDMAC_STAT_RESET);