sys/arch/amiga/dev/clock.c

512

register struct clkreg *clk = (struct clkreg *)clkstd[0];

sys/arch/amiga/dev/clock.c

526

register struct clkreg *clk = (struct clkreg *)clkstd[0];

sys/arch/arm/samsung/exynos_soc.c

711

uint32_t phypwr, rstcon, clkreg;

sys/arch/arm/samsung/exynos_soc.c

714

clkreg = FSEL_CLKSEL_24M;

sys/arch/arm/samsung/exynos_soc.c

716

USB_PHYCLK, clkreg);

sys/arch/hp300/hp300/clock.c

109

volatile struct clkreg *clk;

sys/arch/hp300/hp300/clock.c

114

clk = (volatile struct clkreg *)clkstd[0];

sys/arch/hp300/hp300/clock.c

192

volatile struct clkreg *clk;

sys/arch/hp300/hp300/clock.c

203

clk = (volatile struct clkreg *)clkstd[0];

sys/arch/hp300/hp300/clock.c

286

volatile struct clkreg *clk;

sys/arch/hp300/hp300/clock.c

289

clk = (volatile struct clkreg *)clkstd[0];

sys/arch/hp300/hp300/clock.c

314

volatile struct clkreg *clk;

sys/arch/hp300/hp300/clock.c

319

clk = (volatile struct clkreg *)clkstd[0];

sys/arch/hpcmips/dev/plumpower.c

129

plumreg_t pwrreg, clkreg;

sys/arch/hpcmips/dev/plumpower.c

132

clkreg = plum_conf_read(regt, regh, PLUM_POWER_CLKCONT_REG);

sys/arch/hpcmips/dev/plumpower.c

157

clkreg |= PLUM_POWER_CLKCONT_IO5CLK;

sys/arch/hpcmips/dev/plumpower.c

172

clkreg |= PLUM_POWER_CLKCONT_USBCLK1;

sys/arch/hpcmips/dev/plumpower.c

177

clkreg &= ~PLUM_POWER_CLKCONT_USBCLK2;

sys/arch/hpcmips/dev/plumpower.c

180

clkreg |= PLUM_POWER_CLKCONT_SMCLK;

sys/arch/hpcmips/dev/plumpower.c

183

clkreg |= PLUM_POWER_CLKCONT_PCCCLK1;

sys/arch/hpcmips/dev/plumpower.c

186

clkreg |= PLUM_POWER_CLKCONT_PCCCLK2;

sys/arch/hpcmips/dev/plumpower.c

191

plum_conf_write(regt, regh, PLUM_POWER_CLKCONT_REG, clkreg);

sys/arch/hpcmips/dev/plumpower.c

205

plumreg_t pwrreg, clkreg;

sys/arch/hpcmips/dev/plumpower.c

208

clkreg = plum_conf_read(regt, regh, PLUM_POWER_CLKCONT_REG);

sys/arch/hpcmips/dev/plumpower.c

226

clkreg &= ~PLUM_POWER_CLKCONT_IO5CLK;

sys/arch/hpcmips/dev/plumpower.c

239

clkreg &= ~(PLUM_POWER_CLKCONT_USBCLK1 |

sys/arch/hpcmips/dev/plumpower.c

243

clkreg &= ~PLUM_POWER_CLKCONT_SMCLK;

sys/arch/hpcmips/dev/plumpower.c

246

clkreg &= ~PLUM_POWER_CLKCONT_PCCCLK1;

sys/arch/hpcmips/dev/plumpower.c

249

clkreg &= ~PLUM_POWER_CLKCONT_PCCCLK2;

sys/arch/hpcmips/dev/plumpower.c

254

plum_conf_write(regt, regh, PLUM_POWER_CLKCONT_REG, clkreg);

sys/arch/mips/ingenic/apbus.c

253

aa.aa_clockreg = adv->clkreg;

sys/arch/mips/ingenic/apbus.c

71

uint32_t clkreg; /* CGU register */

sys/arch/x68k/x68k/clock.c

342

struct clkreg *clk = (struct clkreg *)clkstd[0];

sys/arch/x68k/x68k/clock.c

356

struct clkreg *clk = (struct clkreg *)clkstd[0];

sys/dev/pci/if_bnx.c

734

uint32_t clkreg;

sys/dev/pci/if_bnx.c

738

clkreg = REG_RD(sc, BNX_PCICFG_PCI_CLOCK_CONTROL_BITS);

sys/dev/pci/if_bnx.c

740

clkreg &= BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET;

sys/dev/pci/if_bnx.c

741

switch (clkreg) {