sys/arch/arm/nvidia/tegra124_car.c

814

error = clk_set_parent(clk, clk_parent);

sys/arch/arm/nvidia/tegra210_car.c

838

error = clk_set_parent(clk, clk_parent);

sys/arch/arm/nvidia/tegra_drm_mode.c

338

error = clk_set_parent(sc->sc_clk_dc[index],

sys/arch/arm/nvidia/tegra_drm_mode.c

874

error = clk_set_parent(sc->sc_clk_hdmi, sc->sc_clk_hdmi_parent);

sys/arch/arm/nxp/imx6_ccm.c

146

int error = clk_set_parent(clk, clk_parent);

sys/arch/arm/rockchip/rk3399_cru.c

1152

error = clk_set_parent(&clk->base, &pclk->base);

sys/arch/arm/sunxi/sun4i_a10_ccu.c

762

error = clk_set_parent(&clk->base, clkp);

sys/arch/arm/sunxi/sun4i_a10_ccu.c

837

error = clk_set_parent(&clk->base, clkp);

sys/arch/arm/sunxi/sun4i_a10_ccu.c

891

error = clk_set_parent(clk, clkp);

sys/arch/arm/sunxi/sun4i_a10_ccu.c

894

error = clk_set_parent(clk, clkp);

sys/arch/arm/sunxi/sun50i_a64_ccu.c

640

clk_set_parent(&sc->sc_clks[A64_CLK_DE].base, &sc->sc_clks[A64_CLK_PLL_DE].base);

sys/arch/arm/sunxi/sun50i_a64_ccu.c

648

clk_set_parent(&sc->sc_clks[A64_CLK_TCON1].base, &sc->sc_clks[A64_CLK_PLL_VIDEO1].base);

sys/arch/arm/sunxi/sun50i_a64_ccu.c

651

clk_set_parent(&sc->sc_clks[A64_CLK_HDMI].base, &sc->sc_clks[A64_CLK_PLL_VIDEO1].base);

sys/arch/arm/sunxi/sunxi_ccu_display.c

137

error = clk_set_parent(&clk->base, clkp);

sys/arch/arm/sunxi/sunxi_ccu_display.c

65

error = clk_set_parent(&clk->base, &pllclk_x2->base);

sys/arch/arm/sunxi/sunxi_ccu_display.c

70

error = clk_set_parent(&clk->base, clkp);

sys/arch/arm/sunxi/sunxi_ccu_div.c

130

return clk_set_parent(&clk->base, best_parent);

sys/arch/arm/sunxi/sunxi_hdmi.c

606

error = clk_set_parent(sc->sc_clk_mod, clk);

sys/arch/arm/ti/ti_comp_clock.c

185

return clk_set_parent(clk, parent_clk);

sys/dev/clk/clk.h

42

int clk_set_parent(struct clk *, struct clk *);

sys/dev/fdt/fdt_clock.c

248

error = clk_set_parent(clk, clk_parent);