clk_div
u_int period, duty, clk_div, hi, lo;
clk_div = __SHIFTOUT(val, MESON_PWM_MISC_AB_A_CLK_DIV);
clk_div = __SHIFTOUT(val, MESON_PWM_MISC_AB_B_CLK_DIV);
clk_div += 1;
duty_hz = (uint64_t)hi * clk_div;
period_hz = (uint64_t)(hi + lo) * clk_div;
u_int period, duty, clk_div, hi, lo;
clk_div = 1;
clk_div = (period_hz + 0x7fff) / 0xffff;
period_hz /= clk_div;
duty_hz /= clk_div;
clk_div -= 1; /* the divider is N+1 */
if (clk_div > MESON_CLKDIV_MAX)
val |= __SHIFTIN(clk_div, MESON_PWM_MISC_AB_A_CLK_DIV);
val |= __SHIFTIN(clk_div, MESON_PWM_MISC_AB_B_CLK_DIV);
sc->sc_clkfreq / (clk_div + 1), hi, lo, hi * 100 / (hi + lo));
const u_int clk_div = __SHIFTOUT(clkc, SD_CLKC_CLK_DIV);
const u_int act_freq = pll_freq / clk_div;
u_int pll_freq, clk_div;
clk_div = howmany(pll_freq, freq);
clkc |= __SHIFTIN(clk_div - 1, SD_CLKC_CLK_DIV);
u_int ph, rx_phase, clk_div;
clk_div = __SHIFTOUT(clkc, SD_CLKC_CLK_DIV);
for (ph = 0; ph <= clk_div; ph++) {
int clk_div;
clk_div = howmany(pll_freq, freq);
conf |= __SHIFTIN(clk_div - 1, SDIO_CONF_COMMAND_CLK_DIV);
int clk_div, div, diff, best_diff;
clk_div = 255;
clk_div = div;
if (clk_div == 255) {
(clk_div << CTRL_DIV_SHIFT);
u_int clk_div, ciu_div;
clk_div = howmany(pll_freq, freq * ciu_div);
clk_div = 0;
MMC_WRITE(sc, DWC_MMC_CLKDIV, clk_div);
u_int pll_freq, clk_div;
clk_div = (howmany(pll_freq, freq) >> 1) - 1;
clock |= __SHIFTIN(clk_div, MMCI_CLOCK_CLKDIV);