cardbus_conf_write
cardbus_conf_write(cc, cf, tag, offset + PCI_PMCSR, value);
cardbus_conf_write(cc, cf,tag, (off * 4), pcs->reg[off]);
cardbus_conf_write(cc, cf, tag, reg, 0);
cardbus_conf_write(cc, cf, tag, reg, exrom | 1);
cardbus_conf_write(cc, cf, tag,
cardbus_conf_write(cc, cf, tag, reg, exrom & ~1);
cardbus_conf_write(cc, cf, tag,
cardbus_conf_write(cc, cf, tag, PCI_COMMAND_STATUS_REG,
cardbus_conf_write(cc, cf, tag, reg, 0);
cardbus_conf_write(cc, cf, tag, PCI_BAR0, 0);
cardbus_conf_write(cc, cf, tag, PCI_BAR1, 0);
cardbus_conf_write(cc, cf, tag, PCI_BAR2, 0);
cardbus_conf_write(cc, cf, tag, PCI_BAR3, 0);
cardbus_conf_write(cc, cf, tag, PCI_BAR4, 0);
cardbus_conf_write(cc, cf, tag, PCI_BAR5, 0);
cardbus_conf_write(cc, cf, tag, CARDBUS_ROM_REG, 0);
cardbus_conf_write(cc, cf, tag, PCI_BHLC_REG, bhlc);
cardbus_conf_write(cc, cf, tag, PCI_COMMAND_STATUS_REG, command);
cardbus_conf_write(cc, cf, tag, reg, 0xffffffff);
cardbus_conf_write(cc, cf, tag, reg, address);
cardbus_conf_write(cc, cf, tag, reg, 0xffffffff);
cardbus_conf_write(cc, cf, tag, reg, address);
cardbus_conf_write(cc, cf, tag, reg, base);
cardbus_conf_write(cc, cf, cardbustag, reg, 0);
#define Cardbus_conf_write(ct, tag, offs, val) (*(ct)->ct_cf->cardbus_conf_write)((ct)->ct_cc, (tag), (offs), (val))
#define cardbus_conf_write(cc, cf, tag, offs, val) ((cf)->cardbus_conf_write)((cc), (tag), (offs), (val))
void (*cardbus_conf_write)(cardbus_chipset_tag_t, pcitag_t,