bcmeth_write_4
bcmeth_write_4(sc, rxq->rxq_reg_rcvaddrlo,
bcmeth_write_4(sc, txq->txq_reg_xmtptr,
bcmeth_write_4(sc, txq->txq_reg_xmtaddrlo,
bcmeth_write_4(sc, GMAC_INTSTATUS, intstatus); /* write 1 to clear */
bcmeth_write_4(sc, GMAC_INTMASK, sc->sc_intmask);
bcmeth_write_4(sc, GMAC_INTMASK, sc->sc_intmask);
bcmeth_write_4(sc, GMAC_INTMASK, sc->sc_intmask);
bcmeth_write_4(sc, GMAC_INTSTATUS, RCVINT);
bcmeth_write_4(sc, GMAC_INTMASK, sc->sc_intmask);
bcmeth_write_4(sc, GMAC_INTMASK, 0); // disable interrupts
bcmeth_write_4(sc, sc->sc_rxq.rxq_reg_rcvctl,
bcmeth_write_4(sc, sc->sc_txq.txq_reg_xmtctl, XMTCTL_DMA_ACT_INDEX
bcmeth_write_4(sc, UNIMAC_FRAME_LEN, sc->sc_maxfrm);
bcmeth_write_4(sc, UNIMAC_MAC_0, (uint32_t)(macstnaddr >> 0));
bcmeth_write_4(sc, UNIMAC_MAC_1, (uint32_t)(macstnaddr >> 32));
bcmeth_write_4(sc, UNIMAC_COMMAND_CONFIG, sc->sc_cmdcfg);
bcmeth_write_4(sc, GMAC_DEVCONTROL, devctl);
bcmeth_write_4(sc, GMAC_INTRCVLAZY, sc->sc_rcvlazy);
bcmeth_write_4(sc, sc->sc_txq.txq_reg_xmtctl,
bcmeth_write_4(sc, sc->sc_rxq.rxq_reg_rcvctl,
bcmeth_write_4(sc, GMAC_INTMASK, sc->sc_intmask);
bcmeth_write_4(sc, rxq->rxq_reg_rcvctl,
bcmeth_write_4(sc, txq->txq_reg_xmtctl,
bcmeth_write_4(sc, GMAC_INTMASK, 0);
bcmeth_write_4(sc, UNIMAC_COMMAND_CONFIG, SW_RESET);
bcmeth_write_4(sc, GMAC_INTSTATUS, ~0);
bcmeth_write_4(sc, UNIMAC_COMMAND_CONFIG, 0);
bcmeth_write_4(sc, rxq->rxq_reg_rcvptr,