bcmeth_read_4
uint32_t rcvsts0 = bcmeth_read_4(sc, rxq->rxq_reg_rcvsts0);
uint32_t s0 = bcmeth_read_4(sc, txq->txq_reg_xmtsts0);
KASSERT((bcmeth_read_4(sc, UNIMAC_COMMAND_CONFIG) & TX_ENA) == 0);
uint32_t intstatus = bcmeth_read_4(sc, GMAC_INTSTATUS);
__func__, intstatus, bcmeth_read_4(sc, GMAC_INTMASK));
uint32_t rcvsts0 = bcmeth_read_4(sc, rxq->rxq_reg_rcvsts0);
bcmeth_read_4(sc, sc->sc_rxq.rxq_reg_rcvptr),
bcmeth_read_4(sc, sc->sc_rxq.rxq_reg_rcvsts0),
bcmeth_read_4(sc, sc->sc_rxq.rxq_reg_rcvsts1));
bcmeth_read_4(sc, sc->sc_txq.txq_reg_xmtptr),
bcmeth_read_4(sc, sc->sc_txq.txq_reg_xmtsts0),
bcmeth_read_4(sc, sc->sc_txq.txq_reg_xmtsts1));
uint32_t intstatus = bcmeth_read_4(sc, GMAC_INTSTATUS);
uint32_t mac0 = bcmeth_read_4(sc, UNIMAC_MAC_0);
uint32_t mac1 = bcmeth_read_4(sc, UNIMAC_MAC_1);
uint32_t devctl = bcmeth_read_4(sc, GMAC_DEVCONTROL);
bcmeth_read_4(sc, sc->sc_txq.txq_reg_xmtctl) | XMTCTL_ENABLE);
bcmeth_read_4(sc, sc->sc_rxq.rxq_reg_rcvctl) | RCVCTL_ENABLE);
bcmeth_read_4(sc, sc->sc_txq.txq_reg_xmtctl),
bcmeth_read_4(sc, sc->sc_rxq.rxq_reg_rcvctl));
bcmeth_read_4(sc, rxq->rxq_reg_rcvctl) & ~RCVCTL_ENABLE);
bcmeth_read_4(sc, txq->txq_reg_xmtctl) & ~XMTCTL_ENABLE);
uint32_t tx0 = bcmeth_read_4(sc, txq->txq_reg_xmtsts0);
uint32_t rx0 = bcmeth_read_4(sc, rxq->rxq_reg_rcvsts0);