sys/arch/arm/nvidia/tegra124_car.c

1066

if (tpll->base_reg == CAR_PLLX_BASE_REG) {

sys/arch/arm/nvidia/tegra124_car.c

1080

base = bus_space_read_4(bst, bsh, CAR_PLLX_BASE_REG);

sys/arch/arm/nvidia/tegra124_car.c

1087

bus_space_write_4(bst, bsh, CAR_PLLX_BASE_REG, base);

sys/arch/arm/nvidia/tegra124_car.c

442

CLK_PLL("pll_x", "clk_m", CAR_PLLX_BASE_REG,

sys/arch/arm/nvidia/tegra210_car.c

1194

if (tpll->base_reg == CAR_PLLX_BASE_REG) {

sys/arch/arm/nvidia/tegra210_car.c

1208

base = bus_space_read_4(bst, bsh, CAR_PLLX_BASE_REG);

sys/arch/arm/nvidia/tegra210_car.c

1215

bus_space_write_4(bst, bsh, CAR_PLLX_BASE_REG, base);

sys/arch/arm/nvidia/tegra210_car.c

471

CLK_PLL("PLL_X", "CLK_M", CAR_PLLX_BASE_REG,