sys/arch/arm/nvidia/tegra124_car.c

1039

if (tpll->base_reg == CAR_PLLU_BASE_REG) {

sys/arch/arm/nvidia/tegra124_car.c

440

CLK_PLL("pll_u", "clk_m", CAR_PLLU_BASE_REG,

sys/arch/arm/nvidia/tegra210_car.c

1161

if (tpll->base_reg == CAR_PLLU_BASE_REG) {

sys/arch/arm/nvidia/tegra210_car.c

469

CLK_PLL("PLL_U", "CLK_M", CAR_PLLU_BASE_REG,

sys/arch/arm/nvidia/tegra210_car.c

945

tegra_reg_set_clear(bst, bsh, CAR_PLLU_BASE_REG, CAR_PLLU_BASE_OVERRIDE, 0);

sys/arch/arm/nvidia/tegra210_car.c

951

tegra_reg_set_clear(bst, bsh, CAR_PLLU_BASE_REG,

sys/arch/arm/nvidia/tegra210_car.c

956

tegra_reg_set_clear(bst, bsh, CAR_PLLU_BASE_REG, CAR_PLLU_BASE_ENABLE, 0);

sys/arch/arm/nvidia/tegra210_car.c

959

val = bus_space_read_4(bst, bsh, CAR_PLLU_BASE_REG);

sys/arch/arm/nvidia/tegra210_car.c

961

tegra_reg_set_clear(bst, bsh, CAR_PLLU_BASE_REG, CAR_PLLU_BASE_CLKENABLE_ICUSB, 0);

sys/arch/arm/nvidia/tegra210_car.c

962

tegra_reg_set_clear(bst, bsh, CAR_PLLU_BASE_REG, CAR_PLLU_BASE_CLKENABLE_HSIC, 0);

sys/arch/arm/nvidia/tegra210_car.c

963

tegra_reg_set_clear(bst, bsh, CAR_PLLU_BASE_REG, CAR_PLLU_BASE_CLKENABLE_USB, 0);

sys/arch/arm/nvidia/tegra210_car.c

971

tegra_reg_set_clear(bst, bsh, CAR_PLLU_BASE_REG, 0, CAR_PLLU_BASE_OVERRIDE);

sys/arch/arm/nvidia/tegra210_car.c

984

tegra_reg_set_clear(bst, bsh, CAR_PLLU_BASE_REG, 0, CAR_PLLU_BASE_CLKENABLE_USB);