sys/arch/arm/nvidia/tegra124_car.c

629

CAR_PLLE_AUX_REG, CAR_PLLE_AUX_CML0_OEN),

sys/arch/arm/nvidia/tegra124_car.c

631

CAR_PLLE_AUX_REG, CAR_PLLE_AUX_CML1_OEN),

sys/arch/arm/nvidia/tegra210_car.c

1011

tegra_reg_set_clear(bst, bsh, CAR_PLLE_AUX_REG, 0, CAR_PLLE_AUX_REF_SEL_PLLREFE);

sys/arch/arm/nvidia/tegra210_car.c

1012

tegra_reg_set_clear(bst, bsh, CAR_PLLE_AUX_REG, 0, CAR_PLLE_AUX_REF_SRC);

sys/arch/arm/nvidia/tegra210_car.c

1044

tegra_reg_set_clear(bst, bsh, CAR_PLLE_AUX_REG, 0, CAR_PLLE_AUX_SS_SWCTL);

sys/arch/arm/nvidia/tegra210_car.c

1045

tegra_reg_set_clear(bst, bsh, CAR_PLLE_AUX_REG, 0, CAR_PLLE_AUX_ENABLE_SWCTL);

sys/arch/arm/nvidia/tegra210_car.c

1046

tegra_reg_set_clear(bst, bsh, CAR_PLLE_AUX_REG, CAR_PLLE_AUX_SS_SEQ_INCLUDE, 0);

sys/arch/arm/nvidia/tegra210_car.c

1047

tegra_reg_set_clear(bst, bsh, CAR_PLLE_AUX_REG, CAR_PLLE_AUX_USE_LOCKDET, 0);

sys/arch/arm/nvidia/tegra210_car.c

1049

tegra_reg_set_clear(bst, bsh, CAR_PLLE_AUX_REG, CAR_PLLE_AUX_SEQ_ENABLE, 0);

sys/arch/arm/nvidia/tegra210_car.c

618

CAR_PLLE_AUX_REG, CAR_PLLE_AUX_CML0_OEN),

sys/arch/arm/nvidia/tegra210_car.c

620

CAR_PLLE_AUX_REG, CAR_PLLE_AUX_CML1_OEN),