aqm_reg_read
aqm_reg_read(sc, IX_QMGR_Q_CONFIG_ADDR_GET(qId)),
v = aqm_reg_read(sc, off);
__func__, qId, sourceId, aqm_reg_read(sc, off), v, off);
uint32_t status = aqm_reg_read(sc, qi->qUOStatRegAddr);
((status = aqm_reg_read(sc, qi->qUOStatRegAddr)) & qi->qOflowStatBitMask)) {
qPtrs = aqm_reg_read(sc, qi->qConfigRegAddr);
*entry = aqm_reg_read(sc, off);
uint32_t status = aqm_reg_read(sc, qi->qUOStatRegAddr);
entry = aqm_reg_read(sc, off);
entry = aqm_reg_read(sc, off);
uint32_t status = aqm_reg_read(sc, qi->qUOStatRegAddr);
status = aqm_reg_read(sc, qi->qStatRegAddr);
if (aqm_reg_read(sc, IX_QMGR_QUEUPPSTAT0_OFFSET)&qi->qStat0BitMask)
if (aqm_reg_read(sc, IX_QMGR_QUEUPPSTAT1_OFFSET)&qi->qStat1BitMask)
return aqm_reg_read(sc, IX_QMGR_Q_CONFIG_ADDR_GET(qId));
, aqm_reg_read(sc, 0x400)
, aqm_reg_read(sc, 0x400+4)
, aqm_reg_read(sc, 0x400+8)
, aqm_reg_read(sc, 0x400+12)
, aqm_reg_read(sc, 0x410)
, aqm_reg_read(sc, 0x410+4)
, aqm_reg_read(sc, 0x410+8)
, aqm_reg_read(sc, 0x410+12)
, aqm_reg_read(sc, 0x420)
, aqm_reg_read(sc, 0x420+4)
, aqm_reg_read(sc, 0x420+8)
, aqm_reg_read(sc, 0x420+12)
, aqm_reg_read(sc, 0x430)
, aqm_reg_read(sc, 0x430+4)
, aqm_reg_read(sc, 0x430+8)
, aqm_reg_read(sc, 0x430+12)
, aqm_reg_read(sc, a)
, aqm_reg_read(sc, a+4)
, aqm_reg_read(sc, a+8)
, aqm_reg_read(sc, a+12)
, aqm_reg_read(sc, a+16)
, aqm_reg_read(sc, a+20)
, aqm_reg_read(sc, a+24)
, aqm_reg_read(sc, a+28)
, aqm_reg_read(sc, a)
, aqm_reg_read(sc, a+4)
, aqm_reg_read(sc, a+8)
, aqm_reg_read(sc, a+12)
, aqm_reg_read(sc, a+16)
, aqm_reg_read(sc, a+20)
, aqm_reg_read(sc, a+24)
, aqm_reg_read(sc, a+28)
intRegVal = aqm_reg_read(sc, IX_QMGR_QINTREG0_OFFSET);
__func__, intRegVal, aqm_reg_read(sc, IX_QMGR_QINTREG1_OFFSET));
v = aqm_reg_read(sc, reg);
__func__, qId, reg, v, aqm_reg_read(sc, reg));
v = aqm_reg_read(sc, reg);
__func__, qId, reg, v, aqm_reg_read(sc, reg));