ad_write
ad_write(&sc->sc_ad, SP_INTERFACE_CONFIG,
ad_write(&sc->sc_ad, SP_INTERFACE_CONFIG, (reg & ~CAPTURE_ENABLE));
ad_write(&sc->sc_ad, SP_INTERFACE_CONFIG,
ad_write(&sc->sc_ad, SP_INTERFACE_CONFIG, (reg & ~PLAYBACK_ENABLE));
ad_write(&sc->sc_ad, SP_INTERFACE_CONFIG,
ad_write(&sc->sc_ad1848, SP_LOWER_BASE_COUNT, 0xff);
ad_write(&sc->sc_ad1848, SP_UPPER_BASE_COUNT, 0xff);
ad_write(&sc->sc_ad1848, SP_INTERFACE_CONFIG, cfg | PLAYBACK_ENABLE);
ad_write(&sc->sc_ad1848, CS_LOWER_REC_CNT, 0xff);
ad_write(&sc->sc_ad1848, CS_UPPER_REC_CNT, 0xff);
ad_write(&sc->sc_ad1848, SP_INTERFACE_CONFIG, cfg | CAPTURE_ENABLE);
ad_write(&sc->sc_ad1848, SP_INTERFACE_CONFIG,
ad_write(&sc->sc_ad1848, SP_INTERFACE_CONFIG,
ad_write(sc, SP_INTERFACE_CONFIG, r);
ad_write(sc, SP_INTERFACE_CONFIG, reg & ~PLAYBACK_ENABLE);
ad_write(sc, SP_INTERFACE_CONFIG, reg & ~CAPTURE_ENABLE);
ad_write(sc, i, ad1848_init_values[i]);
ad_write(sc, SP_INTERFACE_CONFIG, 0); /* disable SINGLE_DMA */
ad_write(sc, i, ad1848_init_values[i]);
ad_write(sc, mixer_channel_info[device].left_reg,
ad_write(sc, mixer_channel_info[device].left_reg,
ad_write(sc, mixer_channel_info[device].left_reg,
ad_write(sc, mixer_channel_info[device].left_reg,
ad_write(sc, mixer_channel_info[device].left_reg,
ad_write(sc, mixer_channel_info[device].left_reg,
ad_write(sc, mixer_channel_info[device].right_reg, reg | 0x80);
ad_write(sc, mixer_channel_info[device].right_reg, reg &~0x80);
ad_write(sc, info->left_reg, reg);
ad_write(sc, info->right_reg, (atten & info->atten_bits) | reg);
ad_write(sc, SP_LEFT_INPUT_CONTROL, (gain & 0x0f) | reg);
ad_write(sc, SP_RIGHT_INPUT_CONTROL, (gain & 0x0f) | reg);
ad_write(sc, SP_LEFT_INPUT_CONTROL,
ad_write(sc, SP_LEFT_INPUT_CONTROL,
ad_write(sc, SP_LEFT_INPUT_CONTROL, (inp|reg));
ad_write(sc, SP_RIGHT_INPUT_CONTROL, (inp|reg));
ad_write(sc, SP_PIN_CONTROL, reg | INTERRUPT_ENABLE);
ad_write(sc, SP_PIN_CONTROL, reg & ~INTERRUPT_ENABLE);
ad_write(sc, SP_CLOCK_DATA_FORMAT, fs);
ad_write(sc, CS_REC_FORMAT, fs);
void ad_write(struct ad1848_softc *, int, int);
ad_write(&sc->sc_ad1848, SP_MISC_INFO, reg | MODE2);
ad_write(&sc->sc_ad1848, SP_PIN_CONTROL, 0);
ad_write(sc, 0, 0x8a);
ad_write(sc, 1, 0x45); /* 0x55 with bit 0x10 clear */
ad_write(sc, 0, 0x65);
ad_write(sc, 1, 0xaa);
ad_write(sc, SP_MISC_INFO, (~tmp) & 0x0f);
ad_write(sc, SP_MISC_INFO, 0); /* Mode2 = disabled */
ad_write(sc, SP_MISC_INFO, MODE2); /* Set mode2, clear 0x80 */
ad_write(sc, 18, 0x88); /* Set I18 to known value */
ad_write(sc, 2, 0x45);
ad_write(sc, 2, 0xaa);
ad_write(sc, SP_MISC_INFO, MODE3);
ad_write(sc, CS_LEFT_LINE_CONTROL, 0xe0);
ad_write(sc, CS_LEFT_LINE_CONTROL, tmp1);
ad_write(sc, CS_LOWER_REC_CNT, blksize & 0xff);
ad_write(sc, CS_UPPER_REC_CNT, blksize >> 8);
ad_write(sc, SP_LOWER_BASE_COUNT, blksize & 0xff);
ad_write(sc, SP_UPPER_BASE_COUNT, blksize >> 8);
ad_write(sc, SP_INTERFACE_CONFIG, CAPTURE_ENABLE|reg);
ad_write(sc, SP_LOWER_BASE_COUNT, blksize & 0xff);
ad_write(sc, SP_UPPER_BASE_COUNT, blksize >> 8);
ad_write(sc, SP_INTERFACE_CONFIG, PLAYBACK_ENABLE|reg);
ad_write(ac, i, sc->sc_codec_scan[i]);
ad_write(&sc->sc_ad1848, SP_LOWER_BASE_COUNT, 0xff);
ad_write(&sc->sc_ad1848, SP_UPPER_BASE_COUNT, 0xff);
ad_write(&sc->sc_ad1848, SP_INTERFACE_CONFIG,
ad_write(&sc->sc_ad1848, SP_INTERFACE_CONFIG,(cfg & ~PLAYBACK_ENABLE));
ad_write(&sc->sc_ad1848, CS_LOWER_REC_CNT, 0xff);
ad_write(&sc->sc_ad1848, CS_UPPER_REC_CNT, 0xff);
ad_write(&sc->sc_ad1848, SP_INTERFACE_CONFIG,
ad_write(&sc->sc_ad1848, SP_INTERFACE_CONFIG, (cfg & ~CAPTURE_ENABLE));